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Data She et, DS 1, M arch 2001
SCOUT-P Siemens Codec with UPNTransceiver PSB 21391 Version 1.3 SCOUT-PX Siemens Codec with UPNTransceiver featuring Speakerphone functionality PSB 21393 Version 1.3
Wired Communications
Never stop thinking.
Edition 2001-03-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2001.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data She et, DS 1, M arch 2001
SCOUT-P Siemens Codec with UPNTransceiver PSB 21391 Version 1.3 SCOUT-PX Siemens Codec with UPNTransceiver featuring Speakerphone functionality PSB 21393 Version 1.3
Wired Communications
Never stop thinking.
PSB 21391 PSB 21393 Revision History: Previous Version: Page 29 59 81 107 143 157 158 163 231 233 236
2001-03-07 Prel. Data Sheet 09.99
DS 1
Subjects (major changes since last revision) Figure with clock signals added BCL=' 0' changed to BCL='1' BCL changed from 'low' to 'high' Note regarding AXI input added Recommendation regarding CRAM programming modified BCL is inverted compared to last description (DS1); figure added 'Rising' BCL edge changed to 'falling' edge Figure 85 modified Timings added Power supply currents added
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
PSB 21391 PSB 21393
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.1.1 2.1.1.1 2.1.2 2.1.3 2.2 2.2.1 2.2.2 2.2.2.1 2.2.2.1.1 2.2.2.1.2 2.2.2.1.3 2.2.2.1.4 2.2.3 2.2.3.1 2.2.3.2 2.2.4 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4.5 2.2.4.6 2.2.5 2.2.5.1 2.2.6 2.2.7 2.2.7.1 2.2.8 2.3 2.3.1 2.3.2 2.3.3 2.3.4
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pin Definitions and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . . .16 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Microcontroller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 IOM-2 Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Looping and Shifting Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Monitoring TIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Synchronous Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Serial Data Strobe Signal and strobed Data Clock . . . . . . . . . . . . . . . . .41 Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Strobed IOM-2 Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 IOM-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 MONITOR Channel Programming as a Master Device . . . . . . . . . . . .51 MONITOR Channel Programming as a Slave Device . . . . . . . . . . . . .51 MONITOR Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 CIC Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Settings after Reset (see also chapter 7.2) . . . . . . . . . . . . . . . . . . . . . . .55 D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 TIC Bus D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . .56 Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . .59 UPN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 UPN Burst Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Scrambler/Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 UPN Transceiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Data Transfer and Delay between IOM and UPN . . . . . . . . . . . . . . . . . .65
2001-03-07
PSB 21391 PSB 21393
Table of Contents 2.3.4.1 2.3.4.2 2.3.4.3 2.3.4.4 2.3.5 2.3.5.1 2.3.5.1.1 2.3.5.1.2 2.3.5.1.3 2.3.5.1.4 2.3.5.1.5 2.3.5.1.6 2.3.5.1.7 2.3.5.1.8 2.3.5.2 2.3.5.2.1 2.3.5.2.2 2.3.6 2.3.7 2.3.8 2.3.8.1 2.3.8.2 2.3.9 2.3.10 2.3.11 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.2 3.3 3.3.1 3.3.1.1 3.3.1.2
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B1-, B2- and D-Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Stop/Go Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Available/Busy Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 T-Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Control of UPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Internal Layer-1 Statemachine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 State Transition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 C/I Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Receive Infos on UPN (Downstream) . . . . . . . . . . . . . . . . . . . . . . .74 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 C/I Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Transmit Infos on UPN (Upstream) . . . . . . . . . . . . . . . . . . . . . . . . .76 Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . .77 External Layer-1 Statemachine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Activation initiated by the Terminal (TE, SCOUT-P(X)) . . . . . . . . . .79 Activation initiated by the Line Termination LT . . . . . . . . . . . . . . . . 80 Level Detection Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 UPN Transceiver Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Test Signals on the UPN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 UPN Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Non-Auto Mode (MDS2-0 = '01x') . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Transparent Mode 0 (MDS2-0 = '110'). . . . . . . . . . . . . . . . . . . . . . . . . . .87 Transparent Mode 1 (MDS2-0 = '111'). . . . . . . . . . . . . . . . . . . . . . . . . . .87 Transparent Mode 2 (MDS2-0 = '101'). . . . . . . . . . . . . . . . . . . . . . . . . . .87 Extended Transparent Mode (MDS2-0 = '100'). . . . . . . . . . . . . . . . . . . .87 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Structure and Control of the Receive FIFO . . . . . . . . . . . . . . . . . . . . . . .88 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Possible Error Conditions during Reception of Frames . . . . . . . . . . . . 91 Data Reception Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Receive Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Structure and Control of the Transmit FIFO . . . . . . . . . . . . . . . . . . . . . .96 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Possible Error Conditions during Transmission of Frames . . . . . . . . .98
2001-03-07
PSB 21391 PSB 21393
Table of Contents 3.3.1.3 3.3.2 3.4 3.5 3.5.1 3.5.2 3.6 3.7 4 4.1 4.1.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.4 4.4.1 4.4.2 4.4.3 4.4.3.1 4.4.3.2 4.4.4 4.4.4.1 4.4.4.2 4.4.4.3 4.4.5 4.4.6 4.5 4.6 4.7 4.8 4.8.1 4.8.1.1 4.8.2 4.8.2.1
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Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Access to IOM Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 HDLC Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Analog Front End (AFE) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 AFE Attenuation Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Signal Processor (DSP) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Programmable Coefficients for Transmit and Receive . . . . . . . . . . . . .113 Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Four Signal Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Sequence Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Control Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Tone Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Tone Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 DTMF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Speakerphone Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Attenuation Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Speakerphone Test Function and Self Adaption . . . . . . . . . . . . . . . . . .124 Speech Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Background Noise Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Speech Comparators (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Speech Comparator at the Acoustic Side (SCAE) . . . . . . . . . . . . . . .128 Speech Comparator at the Line Side (SCLE) . . . . . . . . . . . . . . . . . .131 Automatic Gain Control of the Transmit Direction (AGCX) . . . . . . . .133 Automatic Gain Control of the Receive Direction (AGCR) . . . . . . . . . . .136 Speakerphone Coefficient Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 Controlled Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Voice Data Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 Programming of the Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Indirect Programming of the Codec (SOP, COP, XOP) . . . . . . . . . . . .143 Description of the Command Word (CMDW) . . . . . . . . . . . . . . . . . . .144 Direct Programming of the Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 CRAM Back-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
2001-03-07
PSB 21391 PSB 21393
Table of Contents 4.8.3 5 5.1 5.1.1 5.1.2 5.1.3 6 6.1 6.2 6.3 6.4 6.5 7 7.0.1 7.0.2 7.0.3 7.0.4 7.0.5 7.0.6 7.0.7 7.0.8 7.0.9 7.0.10 7.0.11 7.0.12 7.0.13 7.0.14 7.0.15 7.0.16 7.0.17 7.0.18 7.0.19 7.0.20 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7
Data Sheet
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Reference Tables for the Register and CRAM Locations . . . . . . . . . . .148 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Jitter on IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Jitter on UPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Jitter on MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Undervoltage Detection (VDDDET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Software Reset Register (SRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Pin Behavior during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 XFIFO - Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 ISTAH - Interrupt Status Register HDLC . . . . . . . . . . . . . . . . . . . . . . . .171 MASKH - Mask Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 STAR - Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 CMDR - Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 MODEH - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 EXMR- Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 TIMR - Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 SAP1 - SAPI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 RBCL - Receive Frame Byte Count Low . . . . . . . . . . . . . . . . . . . . . . . .178 SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 RBCH - Receive Frame Byte Count High . . . . . . . . . . . . . . . . . . . . . . .179 TEI1 - TEI1 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 RSTA - Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 TEI2 - TEI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 TMH -Test Mode Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . . .182 CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . .184 CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . . .184 CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . .185 Transceiver, Interrupt and General Configuration Registers . . . . . . . . . . . 186 TR_CONF0 - Transceiver Configuration Register . . . . . . . . . . . . . . . . .186 TR_CONF1 - Receiver Configuration Register . . . . . . . . . . . . . . . . . . .187 TR_CONF2 - Transmitter Configuration Register . . . . . . . . . . . . . . . . .187 TR_STA - Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . . .188 TR_CMD - Transceiver Command Register . . . . . . . . . . . . . . . . . . . . .189 ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . . .190 MASKTR - Mask Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .190
2001-03-07
PSB 21391 PSB 21393
Table of Contents 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 7.3.14 Page
ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 IOM-2 and MONITOR Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . . .196 XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . . .197 CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . . .198 CO_CR - Control Register Codec Data . . . . . . . . . . . . . . . . . . . . . . . . .199 TR_CR - Control Register Transceiver Data . . . . . . . . . . . . . . . . . . . . .199 HCI_CR - Control Register for HDLC and CI1 Data . . . . . . . . . . . . . . .200 MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . . .200 SDSx_CR - Control Register Serial Data Strobe x . . . . . . . . . . . . . . . .201 IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . . .202 MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .204 ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . . .205 MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . .205 SDS_CONF - Configuration Register for Serial Data Strobes . . . . . . . .206 MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . .206 MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . . .206 MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . . .207 MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .208 MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . . .209 Codec Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 General Configuration Register (GCR) . . . . . . . . . . . . . . . . . . . . . . . . .210 Programmable Filter Configuration Register (PFCR) . . . . . . . . . . . . . .211 Tone Generator Configuration Register (TGCR) . . . . . . . . . . . . . . . . . .212 Tone Generator Switch Register (TGSR) . . . . . . . . . . . . . . . . . . . . . . .213 AFE Configuration Register (ACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 AFE Transmit Configuration Register (ATCR) . . . . . . . . . . . . . . . . . . . .215 AFE Receive Configuration Register (ARCR) . . . . . . . . . . . . . . . . . . . .216 Data Format Register (DFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 Data Source Selection Register (DSSR) . . . . . . . . . . . . . . . . . . . . . . . .218 Extended Configuration (XCR) and Status (XSR) Register . . . . . . . . . .219 Mask Channel x Register (MASKxR) . . . . . . . . . . . . . . . . . . . . . . . . . . .220 Test Function Configuration Register (TFCR) . . . . . . . . . . . . . . . . . . . .221 CRAM Control (CCR) and Status (CSR) Register . . . . . . . . . . . . . . . . .221 CRAM (Coefficient RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Data Sheet
2001-03-07
PSB 21391 PSB 21393
Table of Contents 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.7.1 8.1.8 8.1.9 8.2 8.3 8.3.1 8.3.2 8.3.3 9 Page
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Electrical Characteristics (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 DC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 Serial Control Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . . . . .233 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 Undervoltage Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . .234 Electrical Characteristics (Transceiver) 236 Electrical Characteristics (Codec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 Analog Front End Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .240 Analog Front End Output Characteristics . . . . . . . . . . . . . . . . . . . . . . .240 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
Data Sheet
2001-03-07
PSB 21391 PSB 21393
Overview 1 Overview
The SCOUT-P or SCOUT-PX respectively integrates all necessary functions for the completion of a cost effective digital voice terminal solution. Please note: Throughout the whole document "SCOUTTM"refers to "SCOUTTM-P" and "SCOUTTM-PX" The SCOUT combines the functionality of the ARCOFI(R)-BA PSB 2161 (Audio Ringing Codec Filter Basic Function) or ARCOFI(R)-SP PSB 2163 (Audio Ringing Codec Filter with Speakerphone) respectively and the SmartLink-P PSB 2197 (Subscriber Access Controller for UPN Terminals) or ISAC(R)-P TE PSB 2196 (ISDN Subscriber Access Controller for UPN Terminals in TE mode) respectively on a single chip. The SCOUT-P is suited for the use in basic PBX voice terminals just as it is, and in combination with an additional device on the modular IOM(R)-2 interface, in high end featurephones e.g. with acoustic echo cancellation. The SCOUT-PX PSB 21393 is an extended SCOUT-P PSB 21391 which provides the speakerphone performance of the ARCOFI-SP PSB 2163. The transceiver implements the subscriber access functions for a digital terminal to be connected to a two wire UPN interface. It covers complete layer-1 and basic layer-2 functions for digital terminals. The codec performs encoding, decoding, filtering functions and tone generation (ringing, audible feedback tones and DTMF signal). An analog front end offers three analog inputs and two analog outputs with programmable amplifiers. The IOM-2 interface allows a modular design with functional extensions (e.g. acoustic echo cancellation, tip/ring extension, S/T-interface option, terminal repeater) by connecting other voice/data devices to the SCOUT. A serial microcontroller interface (SCI) is supported. A clock signal and a reset input and output pin complete the microcontroller interface. The SCOUT is a CMOS device offered in a P-MQFP-44 package and operates with a 3.3V or 5V supply.
Data Sheet
1
2001-03-07
PSB 21391 PSB 21393
Overview Comparison of the SCOUT with the two chip solution SmartLink -P and ARCOFI-BA; -SP SCOUT Operating modes Supply voltage Technology Package Transceiver Transformer ratio for receiver and transmitter Transceiver Output Driver 1:1 (3.3V) or 2:1 (5V) Slower slew rate compared with SmartLink by slowed down output drivers Test loop2, 3 Serial (SCI) Test loop2, 3 Serial (SCI) 2:1 (5V) TE 3.3V 5 % or 5V 5 % CMOS P-MQFP-44 SmartLink -P / ARCOFI TE, TR, HDLC Cont. 5V 5 % CMOS, BICMOS P-DSO-28 / P-DSO-28
Test loops Microcontroller Interface Microcontroller clock
Provided Provided ( 7.68, 3.84, 0.96MHz, ( 7.68, 3.84, 1,92, 0.96MHz) disabled or 15.36, 7.68, 1.92 MHz, disabled if double clock rate selected) 256 byte (32 byte FIFO, 96 4 controlreg., 2 statusreg., 4 byte configuration, 128 byte byte FIFO / CRAM 12 byte configuration, 128 byte CRAM Indirect and direct addressing (general purpose RAM) Header/ address(command)/data All timeslots; various possibilities of data access Indirect addressing
Register address space
Codec CRAM access (128 byte) Command structure of the register access Controller data access to IOM-2 timeslots Data control and manipulation
SmartLink specific full duplex structure Not provided
Various possibilities of data B-channel mute and loop back control and data manipulation (enable/ disable, shifting, looping, switching)
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Data Sheet
PSB 21391 PSB 21393
Overview SCOUT IOM-2 IOM-2 Interface Double clock (DCL), Double clock (DCL), bit clock (BCL), bit clock pin (BCL), serial data strobe 1 (SDS1) serial data strobe (SDS) serial data strobe 2 (SDS2/ RSTO) Provided (MON0 or 1 or 2) CI0 (4bit), CI1 (4/6bit) Equivalent to SmartLink Possible Provided (HDLC, SDS) Not possible Not provided Not provided CI0 (4bit), CI1 (Status of 3bit) SmartLink -P / ARCOFI
Monitor channel programming C/I channels Layer 1 state machine State machine in software IDSL (144kBit/s) HDLC support
D- and B- channels; D- channel protocol Non-auto mode, transparent mode 0-2, extended transparent mode 64 bytes per direction with programmable FIFO thresholds Provided RST Input VDDDET Watchdog C/I Code Change EAW Pin Software Reset Not provided 2x4 bytes per direction
FIFO size
Undervoltage detection Reset Sources
Provided RST Input VDDDET Watchdog
Pulse width output LCD contrast Codec Analog inputs Band gap reference Max. AFE gain transmit (guaranteed transmission characteristics) Analog gain steps earpiece
Data Sheet
Provided
1 single ended, 2 differential 1 single ended, 2 differential Externally buffered 36 dB differential inputs 24 dB single ended input 3 dB
3
Internally buffered 42 dB differential inputs 24 dB single ended input 6 dB
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PSB 21391 PSB 21393
Overview SCOUT Speakerphone Status indication AGC initialization Voice data manipulation Register status bits Initial value Three party conferencing (adding receive and transmit data) Voice monitoring on IOM-2 A-/-Law, 8 or 16 bit linear Loudspeaker, earpiece Piezo pins Maximum gain Three party conferencing (adding receive data) Voice monitoring on piezo output A-/-Law, 16 bit linear Not provided Loudspeaker, earpiece, piezo pins SmartLink -P / ARCOFI
Voice data formats Tone Generator Output
Mask register for voice data Provided
Direct tone generator output Provided Provided to loudspeaker Tone generator signal is attenuated by -6dB compared to the ARCOFI; extended gain range (-24.5, -27.5dB) in the loudspeaker amplifier control setting Saturation amplification of tone filter, i.e. CRAM Parameter GE As specified Adjusted to fix value
Data Sheet
4
2001-03-07
Siemens Codec with UPNTransceiver SCOUT-P, SCOUT-PX
PSB 21391 PSB 21393
Version 1.3 1.1 Features
CMOS
* Serial control interface (SCI) * IOM-2 interface in TE mode, single/double clock, two serial data strobe signals * Various possibilities of microcontroller data access, data control and data manipulation to all IOM-2 timeslots * Power supply 3.3 V or 5 V * Monitor channel handler (master/slave) * * * *
P-MQFP-44-1
Sophisticated power management for restricted power mode Programmable microcontroller clock output and reset (input/output) pins Undervoltage detection and power-on reset generation Advanced CMOS technology
Transceiver part * Two wire UPN transceiver with 2B+D channels in half-bauded AMI coding. Fully compatible to UP0 but for reduced loop length * Conversion of the frame structure between the UPN interface and IOM-2 * Receive timing recovery * Continuously adapted receive thresholds * Activation and deactivation procedures with automatic activation from power down state * HDLC controller. Operating in non-auto mode, transparent mode 0-2 or extended transparent mode. Access to B1, B2 or D channels or the combination of them e.g. for 144 kbit/s data transmission (2B+D)
Type PSB 21391 PSB 21393
Data Sheet
Package SCOUT-P SCOUT-PX
5
P-MQFP-44-1 P-MQFP-44-1
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PSB 21391 PSB 21393
Overview * FIFO buffer with 64 bytes per direction and programmable FIFO thresholds for efficient transfer of data packets * D-channel access control * Implementation of IOM-2 MONITOR and C/I-channel protocol to control peripheral devices * Realization of layer 1 state machine in software possible * Watchdog timer * Programmable reset sources * Test loops and functions Codec part * * * * * * * * * * Applications in digital terminal equipment featuring voice functions Digital signal processing performs all CODEC functions Fully compatible with the ITU-T G.712 and ETSI (NET33) specification PCM A-Law/-Law (ITU-T G.711) and 8/16-bit linear data; maskable codec data Flexible configuration of all internal functions Three analog inputs for the handset microphone, the speakerphone and the headset Two differential outputs for a handset earpiece (200 ) and a loudspeaker (50 for 5V power supply, 25 for 3.3V power supply) Flexible test and maintenance loopbacks in the analog front end and the digital signal processor Independent gain programmable amplifiers for all analog inputs and outputs Full digital speakerphone (SCOUT-PX PSB 21393 only) and loudhearing support without any external components (speakerphone test and optimization function is available) Enhanced voice data manipulation for features like: - Three-party conferencing - Voice monitoring Two transducer correction filters Side tone gain adjustment Flexible DTMF, tone and ringing generator Direct and indirect CRAM access
*
* * * *
Data Sheet
6
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PSB 21391 PSB 21393
Overview 1.2 Pin Configuration
reserved
reserved
V DDPLL
V DDL
V SSPLL
V SSL
FSC DCL
LIb
33 32 31 30 29 28 27 26 25 24 23 VDDSEL VDDDET VDDA VSSA VREF BGREF AXI MIN2 MIP2 MIN1 MIP1 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 SCOUT-P(X) PSB 21391 (PSB 21393) P-MQFP-44 22 21 20 19 18 17 16 15 14 13 12 DU DD SDX SDR SCLK VSSD VDDD EAW XTAL1 XTAL2 MCLK
LIa
V DDP
V SSP
CS
LSP
LSN
INT
RST RSTO/SDS2 SDS1
mqfp44_pin_upn.vsd
HOP
Figure 1 Pin Configuration
Data Sheet
7
HON
BCL
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PSB 21391 PSB 21393
Overview 1.3 Logic Symbol
IOM-2 Interface
5 VDD VREF BGREF AXI
Analog Front End
MIP1 MIN1
5 VSS VDDSEL DD DU FSC DCL BCL SDS1 RSTO/ SDS2
RST VDDDET LIa UPN Interface MIP2 MIN2 HOP HON LSP LSN CS INT MCLK SCLK SDR SDX LIb XTAL2 15.36 MHz XTAL1 EAW
Serial Control Interface (SCI)
VDD: VSS:
5 separate power pins 5 separate ground pins
(VDDL,VDDD,VDDA,VDDP,VDDPLL) (VSSL,VSSD,VSSA,VSSP,VSSPLL)
logsym_upn.vsd
Figure 2 Logic Symbol of the SCOUT in P-MQFP-44
Data Sheet
8
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PSB 21391 PSB 21393
Overview 1.4 Table 1 Pin No. Symbol Input (I) Output (O) Open Drain (OD) - - - - - - - - - - Function Pin Definitions and Function
Power supply (3.3 V or 5 V 5 %) 31 16 36 1 27 30 17 37 3 26 34
VDDL VDDD VDDA VDDP VDDPLL VSSL VSSD VSSA VSSP VSSPLL
Supply voltage for line driver Supply voltage for digital parts Supply voltage for analog parts Supply voltage for loudspeaker Supply voltage for internal PLL Ground for line driver Ground for digital parts Ground for analog parts Ground for loudspeaker Ground for internal PLL VDD Selection '0': 3.3 V supply voltage '1': 5 V supply voltage IOM-2 Interface Data Downstream Data Upstream Frame Synchronization Clock (8 kHz) Data Clock (double clock, 1.536 MHz) Bit Clock (768kHz) Programmable strobe signal or bit clock Reset Output (active low) Strobe signal for each IOM(R) time slot and/or D channel indication (programmable) RESET Reset (active low) VDD Detection enable (active low)
9 2001-03-07
VDDSEL I
21 22 25 24 23 11 10
DD DU FSC DCL BCL SDS1 RSTO/ SDS2
I/OD/O I/OD/O I/O I/O O O OD O
9 35
RST
I
VDDDET I
Data Sheet
PSB 21391 PSB 21393
Overview Table 1 Pin No. Symbol Input (I) Output (O) Open Drain (OD) I/O I/O OI I I Function
Transceiver 32 33 13 14 15 LIa LIb XTAL2 XTAL1 EAW UPN transceiver Line Interface Oscillator output Oscillator or 15.36 MHz input External Awake. A low level on this input starts the oscillator from the power down state and generates a reset pulse if enabled (see chapter 7.1.10) In addition an interrupt request is generated at pin INT. Microcontroller Interface 7 8 12 18 19 20 CS INT MCLK SCLK SDR SDX I OD O I I OD/O Chip Select (active low) Interrupt request (active low) Microcontroller Clock Clock for the serial control interface Serial Data Receive Serial Data Transmit
Data Sheet
10
2001-03-07
PSB 21391 PSB 21393
Overview Table 1 Pin No. Symbol Input (I) Output (O) Open Drain (OD) O Function
Analog Frontend 38
VREF
2.4V Reference voltage for biasing external circuitry. An external capacity of 100nF has to be connected. Reference Bandgap voltage for internal references. An external capacity of 22nF has to be connected. Single-ended Auxiliary Input Symmetrical differential Microphone Input 1 Symmetrical differential Microphone Input 2 Differential Handset earpiece output for 200 transducers Differential Loudspeaker output for 50 or 25 loudspeaker using a power supply of 5 V or 3.3 V respectively Reserved Pins This input is not used for normal operation and must be connected to VDD. This input is not used for normal operation and must be connected to VSS.
39
BGREF
I/O
40 44 43 42 41 5 6 2 4
AXI MIP1 MIN1 MIP2 MIN2 HOP HON LSP LSN
I I I I I O O O O
28 29
reserved reserved
I I
Data Sheet
11
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PSB 21391 PSB 21393
Overview 1.5 * * * * * * Typical Applications
The SCOUT can be used in a variety of applications like PBX voice terminal (Figure 3) PBX voice terminal with speakerphone (Figure 4) PBX voice terminal as featurephone with acoustic echo cancellation (Figure 5) PBX voice terminal with tip/ring extension (Figure 6) UPN-terminal repeater (Figure 7) UPN-terminal with S/T-interface option (Figure 8)
SCOUT-P
UPN Interface
SCI
C
pbx_voice_upn.vsd
Figure 3 PBX Voice Terminal
Data Sheet
12
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PSB 21391 PSB 21393
Overview
SCOUT-PX
UPN Interface
SCI
C
voice_te_upn.vsd
Figure 4 PBX Voice Terminal with Speakerphone
SCOUT-P
UPN Interface
IOM-2
SCI
ACE
C
vt_ace_upn.vsd
Figure 5 PBX Voice Terminal as Featurephone with Acoustic Echo Cancellation
Data Sheet
13
2001-03-07
PSB 21391 PSB 21393
Overview
SCOUT-PX
UPN Interface
IOM-2
SCI
SLIC
ARCOFI-BA
C
Fax
vt_tipring_upn.vsd
Figure 6 PBX Voice Terminal with Tip/Ring Extension
SCOUT-PX
UPN Interface
IOM-2
SCI
SmartLink-P PSB 2197
TR-Mode
C
UPN Terminal 2
UPN Terminal 1
upn_rep_te_upn.vsd
Figure 7 UPN-Terminal Repeater
Data Sheet
14
2001-03-07
PSB 21391 PSB 21393
Overview
SCOUT-PX
UPN Interface
IOM-2
SCI
S/T Interface
SBCX
PEB 2081
C
upn_te_st_upn.vsd
Figure 8 UPN-Terminal with S/T- Interface Option
Data Sheet
15
2001-03-07
PSB 21391 PSB 21393
Overview 1.6 General Functions and Device Architecture
Figure 9 shows the architecture of the SCOUT containing the following functional blocks: * UPN interface transceiver with SmartLink PSB 2197 or ISAC-P TE PSB 2196 functionality respectively * Serial microcontroller interface * HDLC controller with 64 byte FlFOs per direction and programmable FIFO threshold * IOM-2 handler and interface for terminal application, MONITOR handler * Clock and timing generation * Digital PLL to synchronize IOM-2 to UPN * Reset generation (watchdog timer, under voltage detection) * Analog Front End (AFE) of the codec part * Digital Signal Processor (DSP) for codec/filter functions, tone generation, voice data manipulation and speakerphone function (SCOUT-PX) These functional blocks are described in the following chapters.
Data Sheet
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Overview
VR E F
D ata S ource S election, Voice Data Manipulation (Coding, Mas king, Conferencing)
BGR E F AXI AMI L P-F ilter A/D Dec F requency Correction F ilter Digital Gain Adjus tment ALS LS P LS N D/A AHO HOP HON T one Generator Int Int S peakerphone F unction Dec AINMUX MIP1 MIN1 MIP2 MIN2
VR E F
Codec Data
HDLCData
IOM-2 Interface IOM-2 Handler
T IC B us Data Monitor Data
B CL S DS 1 S DS 2
FSC
D CL
DU
DD
S -Data
C/I-Data
T IC B us Data
Monitor Data
C/I D ata
HDLC HDLC L APD T rans - R ecei- Controller S tatus mitter ver Command R egis ter F IF O X-F IF O R -F IF O Controller
H DL C Control H DL C D ata
Controller D ata Acces s
C/I D ata
- T rans ceiver
LIa
T IC
MONIT OR Handler
C/I
L Ib
U
PN
T rans c. Control / Config.
MUX
S idetone Codec Control / Config.
DPLL
R es et
VDDDE T
XT AL1
Microcontroller Interface
MCLK S CI
OS C
AF E
DS P
S DX S DR S CL K
CS
Interrupt
Generation
XT AL 2
E AW
AR CHIT -U.VS D
Figure 9 Architecture of the SCOUT
RST
MCL K
IN T
VDD DE T
RSTO
VD DS E L
VDD x VS S x
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Interfaces 2 Interfaces
The SCOUT provides the following interfaces: * Serial microcontroller interface together with a reset and microcontroller clock generation. * IOM-2 interface as an universal backplane for terminals * UPN interface towards the two wire subscriber line * Analog Front End (AFE) as interface between the analog transducers and the digital signal processor of the codec part The microcontroller and IOM-2 interface are described in chapter 2.1 or 2.2 respectively. The UPN interface is described in the chapter 2.3, the analog front end (AFE) in chapter 4.1
Data Sheet
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Interfaces 2.1 Microcontroller Interface
The SCOUT supports a serial microcontroller interface. For applications where no controller is connected to the SCOUT microcontroller interface programming is done via the IOM-2 MONITOR channel from a master device. In such applications the SCOUT operates in the IOM-2 slave mode (refer to the corresponding chapter of the IOM-2 MONITOR handler). The interface selections are all done by pinstrapping. The possible interface selections are listed in table 2. The selection pins are evaluated when the reset input RST or a reset of the undervoltage detection is released. For the pin levels stated in the tables the following is defined: 'High': dynamic pin value which must be 'High' when the pin level is evaluated VDD, VSS: static 'High' or 'Low' level Table 2 Interface Selection PIN CS `High' VSS Interface Type/Mode Serial Control Interface (SCI) IOM-2 MONITOR Channel (Slave Mode)
The mapping of all accessible registers can be found in figure 82 in chapter 7. The microcontroller interface also consists of a microcontroller clock generation at pin MCLK and an interrupt request at pin INT.
Data Sheet
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Interfaces 2.1.1 Serial Control Interface (SCI)
The serial control interface (SCI) is compatible to the SPI interface of Motorola or Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data are transferred via the lines SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning of a serial access to the registers. Incoming data is latched at the rising edge of SCLK and shifts out at the falling edge of SCLK. Each access must be terminated by a rising edge of CS. Data is transferred in groups of 8 bits with the MSB first. Figure 10 shows the timing of a one byte read/write access via the serial control interface.
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Interfaces
Figure 10 Serial Control Interface Timing
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Interfaces 2.1.1.1 Programming Sequences
The principle structure of a read/write access to the SCOUT registers via the serial control interface is shown in figure 11. write sequence: SDR
7
write
byte 2 header
byte 3
write data 0 7 0
0
07
address (command) 6
read sequence: SDR
7
read
byte 2 header
1
07
address (command) 6 0 7
byte 3
read data
0
SDX
Figure 11 Serial Command Structure A new programming sequence starts with the transfer of a header byte. The header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the SCOUT. The possible sequences are listed in table 3 and are described afterwards. Table 3 Header Byte Code Header Byte 00H 08H 40H 44H 48H 4CH Adr-Data-Adr-Data interleaved Sequence Sequence Type Access to Codec reg./CRAM (indirect)
Cmd-Data-Data-Data ARCOFI compatible, non-interleaved ARCOFI compatible, interleaved non-interleaved
Address Range 00H-6FH CRAM (80H-FFH) Address Range 00H-6FH CRAM (80H-FFH)
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Interfaces Table 3 Header Byte Code 4AH 4EH 43H 41H 49H Adr-Data-Data-Data Read-/Write-only Read-/Write-only non-interleaved interleaved Address Range 00H-6FH Address Range 00H-6FH (address autoincrement) CRAM (80H-FFH)
Header 00H: ARCOFI Compatible Sequence This programming sequence is compatible to the SOP, COP and XOP command sequences of the ARCOFI. It gives indirect access to the codec registers 60H-6FH and the CRAM (80H-FFH). The codec command word (cmdw) is followed by a defined number of data bytes (data n; n = 0, 1, 4 or 8). The number of data bytes depends on the codec command word. The commands can be applied in any order and number. The coding of the different SOP, COP and XOP commands is listed in the description of the command word (CMDW) in chapter 4.8. Structure of the ARCOFI compatible sequence:
defined length defined length cmd data n data 1
00H
cmdw
data n
data 1
Header 40H, 44H: Non-interleaved A-D-A-D Sequences The non-interleaved A-D-A-D sequences give direct read/write access to the address range 00H-6FH (header 40H) or the CRAM range 80H-FFH (header 44H) respectively and can have any length. In this mode SDX and SDR can be connected together allowing data transmission on one line. Example for a read/write access with header 40H or 44H: SDR SDX
header wradr wrdata rdadr rddata rdadr rdata wradr wrdata
Data Sheet
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Interfaces Header 48H, 4CH: Interleaved A-D-A-D Sequences The interleaved A-D-A-D sequences give direct read/write access to the address range 00H-6FH (header 48H) or the CRAM range 80H-FFH (header 4CH) respectively and can have any length. This mode allows a time optimized access to the registers by interleaving the data on SDX and SDR. Example for a read/write access with header 48H or 4CH: SDR SDX
header wradr wrdata rdadr rdadr rddata wradr rddata wrdata
Header 4AH, 4EH: Read-/Write-only A-D-D-D Sequences (Address Auto increment) The A-D-D-D sequences give a fast read-/write-only access to the address range 00H6FH (header 4AH) or the CRAM range 80H-FFH (header 4EH) respectively. The starting address (wradr, rdadr) is incremented automatically after every data byte. The sequence can have any length and is terminated by the rising edge of CS. Example for a write access with header 4AH or 4EH: SDR SDX Example for a read access with header 4AH or 4EH: SDR SDX
header rdadr rddata
(rdadr)
header
wradr
wrdata
(wradr)
wrdata
(wradr+1)
wrdata
(wradr+2)
wrdata
(wradr+3)
wrdata
(wradr+4)
wrdata
(wradr+5)
wrdata
(wradr+6)
rddata
(rdadr+1)
rddata
(rdadr+2)
rddata
(rdadr+3)
rddata
(rdadr+4)
rddata
(rdadr+5)
rddata
(rdadr+6)
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Interfaces Header 43H: Read-/Write- only A-D-D-D Sequence This mode (header 43H) can be used for a fast access to the HDLC FIFO data. Any address (rdadr, wradr) in the range between 00h and 1F gives access to the current FIFO location selected by an internal pointer which is automatically incremented with every data byte following the first address byte. The sequence can have any length and is terminated by the rising edge of CS. Example for a write access with header 43H: SDR SDX Example for a read access with header 43H: SDR SDX
header rdadr rddata
(rdadr)
header
wradr
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
rddata
(rdadr)
rddata
(rdadr)
rddata
(rdadr)
rddata
(rdadr)
rddata
(rdadr)
rddata
(rdadr)
Header 41H: Non-interleaved A-D-D-D Sequence This sequence (header 41H) allows in front of the A-D-D-D write access a noninterleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Example for a read/write access with header 41H: SDR SDX
header rdadr rddata rdadr rddata wradr wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
Header 49H: Interleaved A-D-D-D Sequence This sequence (header 49H) allows in front of the A-D-D-D write access an interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of the CS line. Example for a read/write access with header 49H: SDR SDX
header rdadr rdadr rddata wradr rddata wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
Data Sheet
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Interfaces 2.1.2 Interrupt Structure and Logic
Special events in the SCOUT are indicated by means of a single interrupt output, which requests the host to read status information from the SCOUT or transfer data from/to the SCOUT. Since only one INT request output is provided, the cause of an interrupt must be determined by the host reading the interrupt status registers of the SCOUT. The structure of the interrupt status registers is shown in figure 12. MSTI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 MASK ST CIC TIN WOV TRAN MOS HDLC ISTA ST CIC TIN WOV TRAN MOS HDLC CI1E CIX1 STI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 CIC0 CIC1 CIR0 MASKTR LD RIC MRE RME RPF RFO XPR XMR XDU RME RPF RFO XPR XMR XDU MIE MOCR ISTATR LD RIC MDR MER MDA MAB MOSR ASTI
ACK21 ACK20 ACK11 ACK10
INT
MASKH Figure 12 SCOUT Interrupt Status Registers
Data Sheet 26
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Interfaces Five interrupt bits in the ISTA register point at interrupt sources in the HDLC Controller (HDLC), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN) and the synchronous transfer (ST). The timer interrupt (TIN) and the watchdog timer overflow (WOV) can be read directly from the ISTA register. All these interrupt sources are described in the corresponding chapters. After the SCOUT has requested an interrupt by setting its INT pin to low, the host must read first the SCOUT interrupt status register (ISTA) in the associated interrupt service routine. The INT pin of the SCOUT remains active until all interrupt sources are cleared by reading the corresponding interrupt register. Therefore it is possible that the INT pin is still active when the interrupt service routine is finished. Each interrupt indication of the interrupt status registers can selectively be masked by setting the respective bit in the MASK register. For some interrupt controllers or hosts it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. This can be done by masking all interrupts at the end of the interrupt service routine (writing FFH into the MASK register) and write back the old mask to the MASK register. A low level at pin EAW generates an interrupt indication which is set at the LD bit of the ISTATR register. If this LD bit has been set due to an level detect interrupt, the LD bit in the transceiver status register TR_STA is set additionally. Therefore pin EAW has to be connected to '1', if no interrupt should be generated.
Data Sheet
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Interfaces 2.1.3 Microcontroller Clock Generation
The microcontroller clock is provided by the pin MCLK. Five clock rates are selectable by a programmable prescaler (see chapter clock generation figure 78) which is controlled by the MODE1.MCLK bit corresponding following table. By setting the clock divider selection bit (MODE1.CDS) a doubled MCLK frequency is available. The possible MCLK frequencies are listed in table 4. Table 4 MCLK Frequencies MCLK Bits '00' '01' '10' '11' MCLK Frequency with MODE1.CDS = '0' 3.84 MHz (default) 0.96 MHz 7.68 MHz disabled MCLK Frequency with MODE1.CDS = '1' 7.68 MHz (default) 1.92 MHz 15.36 MHz disabled
The clock rate is changed after CS becomes inactive.
Data Sheet
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Interfaces 2.2 IOM-2 Interface
The SCOUT supports the IOM-2 interface in terminal mode with single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge of FSC indicates the start of an IOM-2 frame. The FSC signal is generated by the receive DPLL which synchronizes to the received line frame. The DCL and the BCL output clock signals synchronize the data transfer on both data lines. The DCL is twice the bit rate, the BCL output rate is equal to the bit rate. The bits are shifted out with the rising edge of the first DCL clock cycle and sampled at the falling edge of the second clock cycle. The BCL clock together with the two serial data strobe signals (SDS1, SDS2) can be used to connect time slot oriented standard devices to the IOM-2 interface. The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR register. The BCL clock output can be enabled separately with the EN_BCL bit. The clock rate or frequency respectively of the IOM-signals in TE mode are: DD, DU: 768 kbit/s DCL: 1536 kHz (double clock rate); 768 kHz (single clock rate if DIS_TR = '1') FSC: 8 kHz. If the transceiver is disabled (TR_CONF.DIS_TR) the DCL and FSC pins become input and the HDLC and codec parts can still work via IOM-2. In this case it can be selected with the clock mode bit (IOM_CR.CLKM) between a double clock and a single clock input. Note: One IOM-2 frame has to consist of a multiple of 64 (32) DCL clocks for a double (single) clock selection.
FSC DCL BCL
Figure 13 Clock waveforms
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Interfaces 2.2.1 IOM-2 Frame Structure
The frame structure on the IOM-2 data ports (DU,DD) in IOM-2 terminal mode is shown in figure 14 .
Figure 14 IOM-2 Frame Structure in Terminal Mode The frame is composed of three channels * Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of the layer-1 transceiver. * Channel 1 contains two 64-kbit/s intercommunication channels (IC) plus a MONITOR and command/indicate channel (MON1, CI1) to program or transfer data to other IOM2 devices. * Channel 2 is used for the TlC-bus access. Additionally channel 2 supports further IC and MON channels. Note: Each octet related to any integrated functional block can be programmed to any timeslot (see chapter 7.2.2) except the C/I0- and D- channels that are always related to timeslot 0.
Data Sheet
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Interfaces 2.2.2 IOM-2 Handler
The IOM-2 handler offers a great flexibility for handling the data transfer between the different functional units of the SCOUT and voice/data devices connected to the IOM-2 interface. Additionally it provides a microcontroller access to all time slots of the IOM-2 interface via the four controller data access registers (CDA). Figure 15 shows the architecture of the IOM-2 handler. For illustrating the functional description it contains all configuration and control registers of the IOM-2 handler. A detailed register description can be found in chapter 7.2 The PCM data of the functional units * Codec (CO) * Transceiver (TR) and the * Controller data access (CDA) can be configured by programming the time slot and data port selection registers (TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can be assigned to each of the 12 PCM time slots of the IOM-2 frame. With the DPS bit (Data Port Selection) the output of each functional unit is assigned to DU or DD respectively. The input is assigned vice versa. With the control registers (CR) the access to the data of the functional units can be controlled by setting the corresponding control bits ( EN, SWAP). To avoid data collisions it has to be noticed that the C/I and D channels of the enabled transceiver are always related to time slot 3. If the monitor handler is enabled its data is related to time slot TS (2, 6 or 10) and the appropriate MR and MX bits to time slot TS+1 depending on the MCS bits of register MON_CR. The IOM-2 handler provides also access to the * MONITOR channel (MON) * C/I channels (CI0,CI1) * TIC bus (TIC) and * D- and B-channel for HDLC control The access to these channels is controlled by the registers HCI_CR and MON_CR. The IOM-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the control registers IOM_CR, SDS1_CR and SDS2_CR. The reset configuration of the SCOUT IOM-2 handler corresponds to the defined frame structure and data ports in IOM-2 terminal mode (see figure 14).
Data Sheet
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.
Codec Data
CDA Data
CI0 Data
CI1 Data
Monitor Data
T IC B us Data
Codec Data (CO)
32
MON_CR IOM_CR HCI_CR CDA_T S DPxy CDA_CR x MCDA STI MS T I AS T I MON Handler T IC CI0 Data CI1 Microcontroller Interface
CO10R CO11R CO20R CO21R
CDA10 CDA11 CDA20 CDA21
T R _D_R T R _B 1_R T R _B 2_R T R _T S DP_B1 T R _T S DP_B2 T R _CR
CO_T S DPxy CO_CR
x,y = 1 or 2
IOMHAND.VSD
HDLC F IF O
T rans ceiver Data (T R )
Figure 15 Architecture of the IOM Handler
DU DD F S C DCL B CL S DS 1 S DS 2
Controller Data Acces s (CDA) CDA R egis ter Control Control HDL C C/I1 D-, BData Data (DPS ,E N) (E N) Control Data Acces s (T S DP, DPS , E N, S WAP, T BM, MCDA, S T I) Control Monitor T IC Bus Data Dis able (DPS ,E N (T IC_DIS ) MCS )
D/B 1/B 2 Data
B 1/B 2/D - Data C/IO - Data
Data Sheet
IOM-2 Interface
(E N, T LE N, T S S ) DU DD (E N, OD) S DS 1/2_CR IOM_CR DU DD Control T rans ceiver Data Acces s (T S S , DPS , E N) T R _B1_X T R _B2_X T R _D_X
IOM-2 Handler
CO10X CO11X CO20X CO21X
Control Codec Data (T S S , DPS , E N)
Interfaces
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Interfaces 2.2.2.1 Controller Data Access (CDA)
The IOM-2 handler provides with its four controller data access registers (CDA10, CDA11, CDA20, CDA21) a very flexible solution for the access to the 12 IOM-2 time slots by the microcontroller. The functional unit CDA (controller data access) allows with its control and configuration registers * looping of up to four independent PCM channels from DU to DD or vice versa with the four CDA registers * shifting or switching of two independent PCM channels to another two independent PCM channels on both data ports (DU, DD) * monitoring of up to four time slots on the IOM-2 interface simultaneously * microcontroller read and write access to each PCM channel The access principle which is identical for the two channel register pairs CDA10/11 and CDA20/21 is illustrated in figure 16. The index variables x,y used in the following description can be 1 or 2 for x, and 0 or 1 for y. The prefix 'CDA_' from the register names has been omitted for simplification. To each of the four CDAxy data registers a CDA_TSDPxy register is assigned by which the time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the output of the CDAxy register can be assigned to DU or DD respectively. The time slot and data port for the output of CDAxy is always defined by its own CDA_TSDPxy register. The input of CDAxy depends on the SWAP bit in the control registers CRx. If the SWAP bit = '0' the time slot and data port for the input and output of the CDAxy register is defined by its own CDA_TSDPxy register. The data port for the CDAxy input is vice versa to the output setting for CDAxy. If the SWAP bit = '1', the input port and time slot of the CDAx0 is defined by the CDA_TSDP register of CDAx1 and the input port and time slot of CDAx1 is defined by the CDA_TSDP register of CDAx0. The input and output of every CDAxy register can be enabled or disabled by setting the corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is disabled the output value in the register is retained.
Data Sheet
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Interfaces
.
TSa
TSb
DU
Control Register
1
0
CDA_CRx
0
1
Time Slot Selection (TSS)
CDA_TSDPx0
Input Swap (SWAP)
1
CDAx0
1
Data Port Selection (DPS)
0
1
1
0
TSa x = 1 or 2; a,b = 0...11
TSb
IOM_HAND.FM4
Figure 16 Data Access via CDAx0 and CDAx1 register pairs 2.2.2.1.1 Looping and Shifting Data Figure 17 gives examples for typical configurations with the above explained control and configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers TSDPxy or CDAx_CR: a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = '0') b) shifting data from TSa to TSb on DU and DD (SWAP = '1') c) switching data from TSa (DU) to TSb(DD) and TSb (DU) to TSa (DD)
Data Sheet
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Data Port Selection (DPS) DD
1
1
1
CDAx1
1
CDA_TSDPx1
Enable output input (EN_O0) (EN_I0)
Enable input output (EN_I1) (EN_O1)
Time Slot Selection (TSS)
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Interfaces
a) Looping Data TSa TSb DU
CDAx0
CDAx0
.TSS: TSa TSb .DPS '0' '1' .SWAP '0' b) Shifting Data TSa TSb
DD
DU
CDAx0
CDAx0
DD .TSS: TSa .DPS '0' .SWAP c) Switching Data TSa TSb DU TSb '1' '1'
CDAx0
CDAx0
DD .x = 1 or 2 .TSS: TSa .DPS '0' .SWAP TSb '0' '1'
Figure 17 Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting Data c) Switching Data
Data Sheet
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Interfaces 2.2.2.1.2 Monitoring Data Figure 18 gives an example for monitoring of two IOM-2 time slots each on DU or DD simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd numbers TS(2m+1) (n,m = 0...5). The user has to take care of this restriction by programming the appropriate time slots. . a) Monitoring Data EN_O: '0' CDA_CR1. EN_I: '1' DPS: '0' TSS: TS(2n) '0' '1' '0' TS(2m+1) DU
CDA10 CDA20
CDA11 CDA21
TSS: TS(2n) DPS: '1' CDA_CR2. EN_I: '1' EN_O: '0' Figure 18 Example for Monitoring Data 2.2.2.1.3 Monitoring TIC Bus
TS(2m+1) '1' '1' '0'
DD
n,m = 0...5
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring) bit in the control registers CRx. The TSDPx0 must be set to 08h for monitoring from DU or 88h for monitoring from DD respectively.
Data Sheet
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Interfaces 2.2.2.1.4 Synchronous Transfer While looping, shifting and switching (see figure 21 and 22) the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt (STOV). The microcontroller access to the CDAxy registers can be synchronized by means of four programmable synchronous transfer interrupts (STIxy) and synchronous transfer overflow interrupts (STOVxy) in the STI register. Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is generated two (for DPS='0') or one (for DPS='1') BCL clock after the selected time slot (CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks. A non masked synchronous transfer overflow (STOVx0y0) interrupt is generated if the appropriate STIx1y1 is not acknowledged in time. The STIx1y1 is acknowledged in time if bit ACKx1y1 in the ASTI register is set to '1' one BCL clock (for DPS='0') or zero BCL clocks (for DPS='1') before the time slot which is selected for the appropriate STOVx0y0. If STIx1y1 and STOVx1y1 are not masked STOVx1y1 is only related to STIx1y1 (see example a), c) and d) of figure 20). If STIx1y1 is masked but STOVx1y1 is not masked, STOVx0y0 is related to each enabled STIxy (see example b) and d) of figure 20). Setting the corresponding bits in the MSTI (Mask Synchronous Transfer Interrupts) register masks the STIxy and the STOVxy interrupt. The interrupt structure of the synchronous transfer is shown in figure 19. Examples of the described synchronous transfer interrupt controlling are illustrated in Figure 20. A read to the STI register clears the STIxy and STOVxy interrupts.
.
INT
ST CIC TIN WOV TRAN MOS HDLC MASK
ST CIC TIN WOV TRAN MOS HDLC ISTA
STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 MSTI
STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 STI
ACK21 ACK20 ACK11 ACK10 ASTI
Figure 19 Interrupt Structure of the Synchronous Data Transfer
Data Sheet
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Interfaces
.
: STI interrupt generated : STOV interrupt generated for a not acknowledged STI interrupt
a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '0' 11 TS1 '1' '1' 21 TS5 '1' '1' 20 TS11 '1' '1'
TS11 TS0 TS1 TS2 TS3
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "last possible CDA access"; MSTI.STI10 and MSTI.STOV20 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '1' 11 TS1 '1' '1' 21 TS5 '1' '1' 20 TS11 '1' '0'
TS11 TS0 TS1 TS2 TS3
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
c) Interrupts for data access to time slot 0 and 1 (B1 and B2 after reset), MSTI.STI10, MSTI.STOV10, MSTI.STI11 and MSTI.STOV11 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '0' 11 TS1 '0' '0' 21 TS5 '1' '1' 20 TS11 '1' '1'
TS11 TS0 TS1 TS2 TS3
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
d) Interrupts for data access to time slot 0 (B1 after reset), STOV20 interrupt used as flag for "last possible CDA access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and MSTI.STOV20 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '0' 11 TS1 '1' '1' 21 TS5 '1' '1' 20 TS11 '1' '0'
TS11 TS0 TS1 TS2 TS3
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
sti_stov.vsd
Figure 20 Examples for the Synchronous Transfer Interrupt Control with one enabled STIxy
Data Sheet
38
2001-03-07
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Interfaces Figure 21 shows the timing of looping TSa on DU to TSa on DD (a = 0...11) via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...11
FSC
DU
TSa
TSa
CDAxy
RD STI WR STI STOV ACK
C
*)
DD
TSa
TSa
*) if access by the C is required
Figure 21 Data Access when Looping TSa from DU to DD
Data Sheet
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Interfaces Figure 22 shows the timing of shifting data from TSa to TSb on DU(DD). In figure 22a) shifting is done in one frame because TSa and TSb didn't succeed direct one another (a,b = 0...9 and b a+2). In figure 22b) shifting is done from one frame to the following frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a).
a) Shifting TSa TSb within one frame (a,b: 0...11 and b a+2)
FSC
DU (DD)
TSa
TSb
TSa
CDAxy STI RD WR STOV STI TSa TSb WR STOV ACK STI
C
*)
b) Shifting TSa TSb in the next frame (a,b: 0...11 and (b = a+1 or b FSC
DU (DD)
TSa
TSb
CDAxy STI RD
ACK C *)
*) if access by the C is required
Figure 22 Data Access when Shifting TSa to TSb on DU (DD)
Data Sheet 40 2001-03-07
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Interfaces 2.2.3 Serial Data Strobe Signal and strobed Data Clock
For time slot oriented standard devices connected to the IOM-2 interface the SCOUT provides two independent data strobe signals SDS1 and SDS2. The SDS2 function is shared with the RSTO function at pin RSTO/SDS2, therefore the SDS2 functionality must be selected by setting the RSS bits in the MODE1 register to '01'. Instead of a data strobe signal a strobed IOM bit clock can be provided on pin SDS1 and SDS2. 2.2.3.1 Serial Data Strobe Signal
The two strobe signals can be generated with every 8-kHz frame and are controlled by the registers SDS1/2_CR. By programming the TSS bits and three enable bits (ENS_TSS, ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM-2 time slots TS, TS+1 and TS+3 and any combination of them. The data strobes for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data strobe for TS+3 is always 2 bits long (bit7, bit6). Figure 23 shows three examples for the generation of a strobe signal. In example 1 the SDS is active during channel B2 on IOM-2 whereas in the second example during IC1 and IC2. The third example shows a strobe signal for 2B+D channels which is used e.g. at an IDSL (144kbit/s) transmission.
Data Sheet
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Interfaces
FSC DD,DU
MM RX MM RX
B1 TS0
B2 TS1
MON0 TS2
D CI0
IC1 TS4
IC2 MON1 TS5 TS6
CI1
TS3
TS7
TS8
TS9
TS10 TS11
TS0
TS1
SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3)
Example 1:
TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 TSS ENS_TSS ENS_TSS+1 ENS_TSS+3
= '0H' = '0' = '1' = '0' = '5H' = '1' = '1' = '0' = '0H' = '1' = '1' = '1'
strobe.vsd
Example 2:
Example 3:
Figure 23 Data Strobe Signal
Data Sheet
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Interfaces 2.2.3.2 Strobed IOM-2 Bit Clock
The strobed IOM bit clock is active during the programmed window (see chapter 7.2.8). Outside the programmed window a '0' is driven. Two examples are shown in figure 24.
FSC DD,DU
MON0 D CI0 M M IC1 RX TS2 TS3 TS4
MM RX
B1 TS0
B2 TS1
IC2 MON1 TS5 TS6
CI1
TS7
TS8
TS9
TS10 TS11
TS0
TS1
SDS1 (Example1) SDS1 (Example2) Setting of SDS1_CR: Example 1: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 = '0H' = '0' = '0' = '1' = '5H' = '1' = '1' = '0'
Example 2:
bcl_strobed.vsd
Figure 24 Strobed IOM Bit Clock. Register SDS_CONF programmed to 01H or 03H
Data Sheet
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2001-03-07
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Interfaces 2.2.4 IOM-2 Monitor Channel
The IOM-2 MONITOR channel (see figure 14) is utilized for information exchange between the SCOUT and other devices connected to the MONITOR channel. The MONITOR channel data can be controlled by the bits in the MONITOR control register (MON_CR). For the MONITOR data one of the three IOM channels can be selected by setting the MONITOR channel selection bits (MCS). The DPS bit in the same register selects between an output on DU or DD respectively and with EN_MON the MONITOR data can be enabled/disabled. The default value is MONITOR channel 0 (MON0) enabled and transmission on DD.
IOM-2 MONITOR Channel IOM-2 MONITOR Channel
V/D Module e.g. ARCOFI-BA PSB 2161
MONITOR Handler
V/D Module e.g. Jade PSB 7238
MONITOR Handler
CODEC
Layer 1
CODEC
Layer 1
SCOUT SCOUT as Master Device C C
SCOUT SCOUT as Slave Device
IOM-2 MONITOR Channel
V/D Module e.g. Jade PSB 7238
MONITOR Handler
CODEC
Layer 1
SCOUT SCOUT as Master Device C C
Data Exchange between two Microcontroller Systems
monappl.vsd
Figure 25 Examples of MONITOR Channel Applications
Data Sheet 44 2001-03-07
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Interfaces The MONITOR channel can be used in following applications which are illustrated in figure 25: * As a master device the SCOUT can program and control other devices attached to the IOM-2 which do not need a microcontroller interface e.g. ARCOFI-BA PSB 2161. This facilitates redesigning existing terminal designs in which e.g. an interface of an expansion slot is realized with IOM-2 interface and monitor programming. * As a slave device the codec and the transceiver part of the SCOUT is programmed and controlled from a master device on IOM-2 (e.g. JADE PSB 7238). This is used in applications where no microcontroller is connected directly to the SCOUT. The HDLC controlling is processed by the master device therefore the HDLC data is transferred via IOM-2 interface directly to the master device. * For data exchange between two microcontroller systems attached to two different devices on one IOM-2 backplane. Use of the MONITOR channel avoids the necessity of a dedicated serial communication path between the two systems. This simplifies the system design of terminal equipment. 2.2.4.1 Handshake Procedure
The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the MONITOR Channel Receive (MR) and MONITOR Channel Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is activated. This data will be transmitted once per 8-kHz frame until the transfer is acknowledged via the MR bit.
Data Sheet
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Interfaces The MONITOR channel protocol is described In the following section and illustrated in Figure 26. The relevant control and status bits for transmission and reception are listed in table 5 and table 6. Table 5 Transmission of MONITOR Data Control/ Status Bit Control Status Register MOCR MOSR MSTA Bit MXC MIE MDA MAB MAC Function MX Bit Control Interrupt (MDA, MAB, MER) Enable Data Acknowledged Interrupt Data Abort Interrupt Transmission Active
Table 6 Reception of MONITOR Data Control/ Status Bit Control Status Register MOCR MOSR Bit MRC MRE MDR MER Function MR Bit Control Receive Interrupt (MDR) Enable Data Received Interrupt End of Reception Interrupt
Data Sheet
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Interfaces
Transmission C MON MIE=1 MOX=ADR MXC=1 MAC=1 FF FF ADR ADR ADR ADR DATA1 DATA1 DATA1 DATA1 DATA2 DATA2 DATA2 DATA2 FF FF FF FF MX 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 MR 1 1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1
Reception C MRE=1 125s
MDA Int. MOX=DATA1
MDR Int. RD MOR (=ADR) MRC=1 MIE=1 MDR Int. RD MOR (=DATA1)
MDA Int. MOX=DATA2
MDR Int. RD MOR (=DATA2)
MDA Int. MXC=0
MER Int. MRC=0
MAC=0
Figure 26 MONITOR Channel Protocol (IOM-2)
Data Sheet
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2001-03-07
PSB 21391 PSB 21393
Interfaces Before starting a transmission, the microcontroller should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a '0' in the MONITOR Channel Active MAC status bit. After having written the MONITOR Data Transmit (MOX) register, the microcontroller sets the MONITOR Transmit Control bit MXC to '1'. This enables the MX bit to go active (0), indicating the presence of valid MONITOR data (contents of MOX) in the corresponding frame. As a result, the receiving device stores the MONITOR byte in its MONITOR Receive MOR register and generates an MDR interrupt status (MRE must be '1'). Alerted by the MDR interrupt, the microcontroller reads the MONITOR Receive (MOR) register. When it is ready to accept data (e.g. based on the value in MOR, which in a point-to-multipoint application might be the address of the destination device), it sets the MR control bit MRC to '1' to enable the receiver to store succeeding MONITOR channel bytes and acknowledge them according to the MONITOR channel protocol. In addition, it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable (MIE) to '1'. As a result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to '0'. This causes a MONITOR Data Acknowledge MDA interrupt status at the transmitter. A new MONITOR data byte can now be written by the microcontroller in MOX. The MX bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR channel by returning the MX bit active after sending it once in the inactive state. As a result, the receiver stores the MONITOR byte in MOR and generates a new MDR interrupt status. When the microcontroller has read the MOR register, the receiver acknowledges the data by returning the MR bit active after sending it once in the inactive state. This in turn causes the transmitter to generate an MDA interrupt status. This "MDA interrupt - write data - MDR interrupt - read data - MDA interrupt" handshake is repeated as long as the transmitter has data to send. When the last byte has been acknowledged by the receiver (MDA interrupt status), the microcontroller sets the MONITOR Transmit Control bit MXC to '0'. This enforces an inactive ('1') state in the MX bit. Two frames of MX inactive signifies the end of a message. Thus, a MONITOR Channel End of Reception MER interrupt status is generated by the receiver when the MX bit is received in the inactive state in two consecutive frames. As a result, the microcontroller sets the MR control bit MRC to 0, which in turn enforces an inactive state in the MR bit. This marks the end of the transmission, making the MONITOR Channel Active MAC bit return to '0'. During a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive MR bit value in two consecutive frames. This is effected by the microcontroller writing the MR control bit MRC to '0'. An aborted transmission is indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter.
Data Sheet
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2001-03-07
PSB 21391 PSB 21393
Interfaces The MONITOR transfer protocol rules are summarized in the following section * A pair of MX and MR in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission. * A start of a transmission is initiated by the transmitter by setting the MXC bit to '1' enabling the internal MX control. The receiver acknowledges the received first byte by setting the MR control bit to '1' enabling the internal MR control. * The internal MX,MR control indicates or acknowledges a new byte in the MON slot by toggling MX,MR from the active to the inactive state for one frame. * Two frames with the MX-bit in the inactive state indicate the end of transmission. * Two frames with the MR-bit set to inactive indicate a receiver request for abort. * The transmitter can delay a transmission sequence by sending the same byte continuously. In that case the MX-bit remains active in the IOM-2 frame following the first byte occurrence. * Since a double last-look criterion is implemented the receiver is able to receive the MON slot data at least twice (in two consecutive frames). The receiver acknowledge the data after the reception of two identical bytes in two successive frames. * To control this handshake procedure a collision detection mechanism is implemented in the transmitter. This is done by making a collision check per bit on the transmitted MONITOR data and the MX bit. * Monitor data will be transmitted repeatedly until its reception is acknowledged or the transmission time-out timer expires. * Two frames with the MX bit in the inactive state indicates the end of a message (EOM). * Transmission and reception of monitor messages can be performed simultaneously. This feature is used by the SCOUT to send back the response before the transmission from the controller is completed (the SCOUT does not wait for EOM from the controller). MONITOR control commands nevertheless are processed sequential that means e.g. during a read on a register no further command is executed. 2.2.4.2 Error Treatment
In case the SCOUT does not detect identical monitor messages in two successive frames, transmission is not aborted. Instead the SCOUT will wait until two identical bytes are received in succession. A transmission is aborted by the SCOUT if * an error in the MR handshaking occurs * a collision on the IOM bus of the MONITOR data or MX bit occurs * the transmission time-out timer expires A reception is aborted by the SCOUT if * an error in the handshaking occurs or * an abort request from the opposite device occurs
Data Sheet 49 2001-03-07
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Interfaces MX/MR Treatment in Error Case: In the master mode the MX/MR bits are under control of the microcontroller through MXC or MRC respectively. An abort is indicated by an MAB interrupt or MER interrupt respectively. In the slave mode the MX/MR bits are under control of the SCOUT. An abort is always indicated by setting the MX/MR bit inactive for two or more IOM-2 frames. The controller must react with EOM. Figure 27 shows an example for an abort requested by the receiver, Figure 28 shows an example for an abort requested by the transmitter and Figure 29 shows an example for a successful transmission.
IOM -2 Frame No. MX (DU)
1
1
2
3
4
5
6 EOM
7
0
MR (DD)
1 0
Abort Request from Receiver
mon_rec-abort.vsd
Figure 27 Monitor Channel, Transmission Abort requested by the Receiver
IOM -2 Frame No. MR (DU)
1
1
2
3
4
5
6 EOM
7
0
MX (DD)
1 0
Abort Request from Transmitter
mon_tx-abort.vsd
Figure 28 Monitor Channel, Transmission Abort requested by the Transmitter
Data Sheet 50 2001-03-07
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Interfaces
IOM -2 Frame No. MR (DU)
1
1
2
3
4
5
6
7 EOM
8
0
MX (DD)
1 0
mon_norm.vsd
Figure 29 Monitor Channel, normal End of Transmission 2.2.4.3 MONITOR Channel Programming as a Master Device
As a master device the SCOUT can program and control other devices attached to the IOM-2 interface. The master mode is selected by default if the microcontroller interface is used. The monitor data is written by the microcontroller in the MOX register and transmitted via IOM-2 DD(DU) line to the programmed/controlled device e.g. ARCOFIBA PSB 2161. The transfer of the commands in the MON channel is regulated by the handshake protocol mechanism with MX, MR which is described in the previous chapters 2.2.4.1 and 2.2.4.2. If the transmitted command was a read command the slave device responds by sending the requested data. The data structure of the transmitted monitor message depends on the device which is programmed. Therefore the first byte of the message is a specific address code which contains in the higher nibble a MONITOR channel address to identify different devices. The length of the messages depends on the accessed device and the command following the address byte. 2.2.4.4 MONITOR Channel Programming as a Slave Device
Applications in which no controller is connected to the SCOUT it must operate in the MONITOR slave mode which can be selected by pinstrapping the microcontroller interface pins according to chapter 2.1. As a slave device the codec and the transceiver part of the SCOUT is programmed and controlled by a master device at the IOM-2 interface. All programming data required by the SCOUT are received in the MONITOR time slot of channel 0 on the IOM-2 and is transferred in the MOR register. The transfer of the commands in the MON channel is regulated by the handshake protocol mechanism with MX, MR which is described in the previous chapters 2.2.4.1 and 2.2.4.2. The first byte of the MONITOR message must contain in the higher nibble the MONITOR
Data Sheet 51 2001-03-07
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Interfaces channel address code which is '1010' for the SCOUT. The lower nibble distinguishes between a programming command or an identification command. Identification Command In order to be able to identify unambiguously different hardware designs of the SCOUT by software, the following identification command is used: DD 1st byte value DD 2nd byte value 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
The SCOUT responds to this DD identification sequence by sending a DU identification sequence: DU 1st byte value DU 2nd byte value 1 1 0 0 1 0 0 0 0 0
DESIGN
DESIGN: six bit code, specific for each device in order to identify differences in operation (see chapter 7.1.12). This identification sequence is usually done once, when the terminal is connected for the first time. This function is used by the software to distinguish between different possible hardware configurations. However this sequence is not compulsory. Programming Sequence The programming sequence is characterized by a '1' being sent in the lower nibble of the received address code. The data structure after this first byte is equivalent to the structure of the serial control interface described in chapter 2.1.1. DD 1st byte value DD 2nd byte value DD 3rd byte value DD 4th byte value DD (nth + 3) byte value R/W 1 0 1 0 0 0 0 1
Header Byte Command/ Register Address Data 1 Data n
All registers can be read back when setting the R/W bit to '1' in the byte for the command/ register address. The SCOUT responds by sending his IOM specific address byte (A1h) followed by the requested data.
Data Sheet
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Interfaces 2.2.4.5 MONITOR Time-Out Procedure
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be enabled by setting the time-out bit (TOUT) in the MONITOR configuration register (MCONF). An internal timer is always started when the transmitter must wait for the reply of the addressed device or for transmit data from the microcontroller. After 40 IOM frames (5ms) without reply the timer expires and the transmission will be aborted. 2.2.4.6 MONITOR Interrupt Logic
Figure 30 shows the MONITOR interrupt structure of the SCOUT. The MONITOR Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER, MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE. MRE inactive (0) prevents the occurrence of MDR status, including when the first byte of a packet is received. When MRE is active (1) but MRC is inactive, the MDR interrupt status is generated only for the first byte of a receive packet. When both MRE and MRC are active, MDR is always generated and all received MONITOR bytes - marked by a 1to-0 transition in MX bit - are stored. (Additionally, an active MRC enables the control of the MR handshake bit according to the MONITOR channel protocol.)
MASK ST CIC TIN WOV TRAN MOS HDLC
ISTA ST CIC TIN WOV TRAN MOS HDLC
MRE MIE MOCR
MDR MER MDA MAB MOSR
INT
Figure 30 MONITOR Interrupt Structure
Data Sheet 53 2001-03-07
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Interfaces 2.2.5 C/I Channel Handling
The Command/Indication channel carries real-time status information between the SCOUT and another device connected to the IOM. 1) One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the layer-2 parts of the SCOUT. It can be accessed by an external layer-2 device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel access may be arbitrated via the TIC bus access protocol. In this case the arbitration is done in C/I channel 2 (see figure 14). The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2) and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits long. A listing and explanation of the layer-1 C/I codes can be found in chapter 2.3.5.1.3 and 2.3.5.1.6. In the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated anytime a change occurs (ISTA.CIC). A new code must be found in two consecutive IOM frames to be considered valid and to trigger a C/ I code change interrupt status (double last look criterion). In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0. 2) A second C/I channel (called C/I1) can be used to convey real time status information between the SCOUT and various non-layer-1 peripheral devices e.g. PSB 2161 ARCOFI-BA. The C/I1 channel consists of four or six bits in each direction.The width can be changed from 4bit to 6bit by setting bit CIX1.CICW. The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received C/I1 code is indicated by an interrupt status without double last look criterion. 2.2.5.1 CIC Interrupt Logic
Figure 31 shows the CIC interrupt structure. A CIC interrupt may originate - from a change in received C/I channel 0 code (CIC0) or - from a change in received C/I channel 1 code (CIC1). The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case the occurrence of a code change in CIR1 will not be displayed by CIC1 until the corresponding enable bit has been set to one. Bits CIC0 and CIC1 are cleared by a read of CIR0. An interrupt status is issued every time a valid new code is loaded into CIR0 or CIR1. The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the received C/I channel 0 before the first one has been read, immediately after reading of CIR0 a new interrupt will be generated and the new code will be stored in CIR0.
Data Sheet 54 2001-03-07
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Interfaces If several consecutive codes are detected, only the first and the last code is obtained at the first and second register read, respectively. For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always stored in CIR1.
MASK ST CIC TIN WOV TRAN MOS HDLC
ISTA ST CIC TIN WOV TRAN MOS HDLC CIC0 CIC1 CIR0
CI1E CIX1
INT Figure 31 CIC Interrupt Structure 2.2.6 Settings after Reset (see also chapter 7.2)
After reset the codec, the TIC-bus access, the serial data strobes (pin SDS1 and SDS2) and the controller data access are disabled. The IOM handler is enabled except the generation of the bit clock (pin BCL). The monitor handler is enabled for channel MON0 and the transceiver for the channels B1, B2, C/I0 and D. The HDLC controller is connected to the D channels. The pins DD and DU are in open drain state. The synchronous transfer interrupts and synchronous transfer overflow interrupts are masked.
Data Sheet
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Interfaces 2.2.7 D-Channel Access Control
D-channel access control was defined to guarantee all connected HDLC controllers a fair chance to transmit data in the D-channel. Collisions are possible on the IOM-2 interface, if there is more than one HDLC controller connected. This arbitration mechanism is implemented in the SCOUT and will be described in the following chapter. 2.2.7.1 TIC Bus D-Channel Access Control
The TIC bus is implemented to organize the access to the layer-1 functions provided in the SCOUT (C/I-channel) and to the D-channel from up to 7 external communication controllers (see figure 32). To this effect the outputs of the controllers (ICC:ISDN Communication Controller PEB 2070) are wired-or and connected to pin DU. The inputs of the ICCs are connected to pin DD. External pull-up resistors on DU/DD are required. The arbitration mechanism must be activated by setting MODEH.DIM2-0=00x.
C-Interface D-channel Telemetry/ Packet Communication IOM-2 Interface
ICC(7)
B-channel Voice/Data Communication with D-channel Signaling
ICC(1)
TIC Bus
UPN-Interface
B-channel Voice/Data Communication with D-channel Signaling
TIC Bus D-channel Access Control
UPN-Transceiver
SCOUT-P(X)
TIC_ARBI-UPN.vsd
Figure 32 Applications of TIC Bus in IOM-2 Bus Configuration
Data Sheet
56
2001-03-07
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Interfaces The arbitration mechanism is implemented in the last octet in IOM channel 2 of the IOM2 interface (see figure 33). An access request to the TIC bus may either be generated by software (P access to the C/I channel) or by the SCOUT itself (transmission of an HDLC frame in the D-channel). A software access request to the bus is effected by setting the BAC bit (CIX0 register) to '1'. In the case of an access request, the SCOUT checks the Bus Accessed-bit BAC (bit 5 of DU last octet of channel 2, see figure 33) for the status "bus free", which is indicated by a logical '1'. If the bus is free, the SCOUT transmits its individual TIC bus address TAD programmed in the CIX0 register and compares it bit by bit with the value on DU. If a sent bit set to '1' is read back as '0' because of the access of another D-channel source with a lower TAD, the SCOUT withdraws immediately from the TIC bus. The TIC bus is occupied by the device which sends its address error-free. If more than one device attempt to seize the bus simultaneously, the one with the lowest address wins and starts D-channel transmission.
MR MX DU
% % 021 ' &, ,& ,& 021 &,
MR MX
TAD BAC
%$&
7$'
TIC-Bus Address (TAD 2-0) Bus Accessed ('1' no TIC-Bus Access)
tic_octet-du.vsd
Figure 33 Structure of Last Octet of Ch2 on DU When the TIC bus is seized by the SCOUT, the bus is identified to other devices as occupied via the DU channel 2 Bus Accessed-bit state '0' until the access request is withdrawn. After a successful bus access, the SCOUT is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. If none of the devices connected to the IOM interface requests access to the D and C/I channels, the TIC bus address 7 will be present. The device with this address will therefore have access, by default, to the D and C/I channels. Note: Bit BAC (CIX0 register) should be reset by the P when access to the C/I channels is no more requested, to grant other devices access to the D and C/I channels.
Data Sheet
57
2001-03-07
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Interfaces The availability of the line interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the DD last octet of channel 2 (figure 34). S/G = 1 : stop S/G = 0 : go
MR MX DD
% % 021 ' &, ,& ,& 021 &,
MR MX
A/B S/G
6*
$%
Available/Blocked Stop/Go
tic_octetdd-upn.vsd
Figure 34 Structure of Last Octet of Ch2 on DD The Stop/Go bit is available to other layer-2 devices connected to the IOM to determine if they can access the D channel of the line interface.
Data Sheet
58
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PSB 21391 PSB 21393
Interfaces 2.2.8 Activation/Deactivation of IOM-2 Interface
The IOM-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. In this deactivated state is FSC = '1', DCL = '0' and BCL = '1' and the data lines are '1'. The data between the functional blocks of the SCOUT is then transferred internally. The IOM-2 interface can be kept active while the line interface is deactivated by setting the CFS bit to "0" (MODE register). This is the case after a hardware reset. If the IOM-2 interface should be switched off while the line interface is deactivated, the CFS bit should be set to '1'. In this case the internal oscillator is disabled when no signal (info 0) is present on the line interface and the C/I command is '1111' = DIU (refer to chapter 2.3.5.1.3 and 2.3.5.1.6). If the TE wants to activate the line, it has first to activate the IOM-2 interface either by using the "Software Power Up" function (IOM_CR.SPU bit) or by setting the CFS bit to "0" again. The deactivation procedure is shown in figure 35. After detecting the code DI (Deactivate Indication) the layer 1 of the SCOUT responds by transmitting DC (Deactivate Confirmation) during subsequent frames and stops the timing signals synchronously with the end of the last C/I (C/I0) channel bit of the 6th frame.
IOM-2
IOM -2 Deactivated
FSC DI DU DI DI DI DI DI DI DI DI DI DI DI
DR DD
DR
DR
DR
DR
DR
DR
DC
DC
DC
DC
DC
DC
B1
B2
D CIO
D
CIO
DCL
ITD09655
Figure 35 Deactivation of the IOM(R)-Interface
Data Sheet
59
2001-03-07
PSB 21391 PSB 21393
Interfaces The clock pulses will be enabled again when the DU line is pulled low (bit SPU in the IOM_CR register) i.e. the C/I command TIM = "0000" is received by layer 1, or when a non-zero level on the line interface is detected. The clocks are turned on after approximately 0.2 to 4 ms depending on the capacitances on XTAL 1/2. DCL is activated such that its first rising edge occurs with the beginning of the bit following the C/I (C/I0) channel. After the clocks have been enabled this is indicated by the PU code in the C/I channel and by a CIC interrupt. The DU line may be released by resetting the Software Power Up bit IOM_CR ='0' and the C/I code written to CIX0 before (e.g. TIM or AR8) is output on DU. The SCOUT supplies IOM timing signals as long as there is no DIU command in the C/ I (C/I0) channel. If timing signals are no longer required and activation is not yet requested, this is indicated by programming DIU in the CIX0 register.
Data Sheet
60
2001-03-07
PSB 21391 PSB 21393
Interfaces
SPU = 1
CIC : CIXO = TIM Int. SPU = 0
FSC TIM DU TIM TIM
~ ~
~ ~
DD
FSC
~ ~
~ ~
PU
PU
PU
PU
PU
~ ~
~~ ~~
DU 0.2 to 4 ms
~ ~
~ ~
IOM -CH1
R
~ ~
IOM -CH2
R
~ ~
B1
~~ ~~
DD
MR MX
IOM -CH1
R
~ ~
IOM -CH2
R
B1
DCL
~ ~
132 x DCL
ITD09656
Figure 36 Activation of the IOM-Interface
Data Sheet 61 2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3 - - - - - - - UPN Interface
The layer-1 functions for the UPN interface of the SCOUT-P(X) are: conversion of the frame structure between IOM and UPN interface conversion from/to binary to/from half-bauded AMI coding level detection receive timing recovery IOM-2 timing synchronous to UPN D channel access control activation/deactivation procedures, triggered by primitives received over the IOM C/I channel or by INFO's received from the line - execution of test loops 2.3.1 UPN Burst Frame
Figure 37 demonstrates the general principles of the UPN interface communication scheme. A frame transmitted by the exchange (LT) is received by the terminal equipment (TE) after a line propagation delay. The terminal equipment waits the minimum guard time (tg = 5.2 s) while the line clears. It then transmits a frame to the exchange. The exchange will begin a transmission every 250 s (known as the burst repetition period). Within a burst, the data rate is 384 kbit/s and the 38-bit frame structure is as shown in figure 37. The framing bit (LF) is always logical `1'. The frame also contains the user channels (2B + D). Note that the B-channels are scrambled. It can readily be seen that in the 250-s burst repetition period, 4 D-bits, 16 B1-bits and 16 B2-bits are transferred in each direction. This gives an effective full duplex data rate of 16 kbit/s for the D-channel and 64 kbit/s for each B-channel. The final bit of the frame is called the M-bit. Four successive M-bits, from four successive UPN frames, constitute a superframe (see figure 37). Three signals are carried in this superframe. The superframe is started by a code violation (CV). From this reference, bit 3 of the superframe is the service channel bit (S). The S-channel bit is transmitted once in each direction in every fourth burst repetition period. Hence the duplex S-channel has a data rate of 1 kbit/s. It conveys test loop control information from the LT to the TE and reports transmission errors from the TE to the LT. Bit 2 and bit 4 of the superframe are the T-bits. In order to decrease DCoffset voltage on the line after transmission of a CV in the M-bit position, it is allowed to add a DC-balancing bit to the burst. The LT-side transmits this DC-balancing bit, when transmitting INFO 4 and when line characteristics indicate potential decrease in performance. Note that the guard time in TE is always defined with respect to the M-bit, whereas AMIcoding includes always all bits going in the same direction. The coding technique used on the UPN interface is half-bauded AMI-code (i.e. with a 50 % pulse width). A logical `0' corresponds to a neutral level, a logical `1' is coded as alternate positive and negative pulses.
Data Sheet
62
2001-03-07
PSB 21391 PSB 21393
Interfaces
tr LT, TR
TE
td
tg
td
LF 1
B1 8
B2 8
D 4 99 s
B1 8
B2 8
M DC 1
CV T S T
ITD05337
Binary Value Line Signal
0
1
0
0
1
1
0
1
0
1 +V 0 -V
CV.
ITD05338
td: line delay tg: guard time (5.2 s) tr: repetition period (250 s) Figure 37 UPN Interface Structure
Data Sheet
63
2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.2 Scrambler/Descrambler
B-channel data on the UPN interface is scrambled to give a flat continuous power density spectrum and to ensure enough pulses are present on the line for a reliable clock extraction to be performed at the downstream end. The SCOUT-P(X) therefore contains a scrambler and descrambler, in the transmit and receive directions respectively. The basic form of these are illustrated in figure 38. The form is in accordance with the CCITT V.27 scrambler/descrambler and contains supervisory circuitry which ensures no periodic patterns appear on the line.
D0 = Di + Ds ( Z -6 + Z -7 ) Scrambler OUT Ds
Z -1
Z -1
Z -1
Z -1
Z -1
Z -1 Ds Z -6
Z -1
Di Scrambler IN
+
Ds Z -6 + Ds Z -7
+
Ds Z -7
ITD05339
Do = Di = Ds (1 + Z -6 + Z -7 ) Descrambler IN Ds
Z -1
Z -1
Z -1
Z -1
Z -1
Z -1 Ds Z -6
Z -1
Do Descrambler OUT
+
Ds Z -6 + Ds Z -7
+
Ds Z -7
ITD05340
Figure 38 Scrambler/Descrambler
Data Sheet
64
2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.3 UPN Transceiver Timing
The receive PLL uses the 15.36-MHz clock to generate an internal 384-kHz signal which is used to synchronize the PLL to the received UPN frame. The PLL outputs the FSCsignal as well as the 1.536-MHz double bit clock signal and the 768-kHz bit clock. The length of the FSC signal pulse is reduced to one DCL period ("Short FSC") at the beginning of the second IOM frame after the received code violation in the M-bit. The reduced length of the FSC-signal provides synchronization between the TE- and the TRtransceiver to gain the shortest delays on the UPN T-channel data forwarding. 2.3.4
Data Transfer and Delay between IOM and UPN
CV UPN B1 B2 D B1 B2 CV B1 B2 D B1 B2 B1 B2 D B1 B2 T B1 B2 D B1 B2 T
FSC
DU B1 B2 D BAC B1 B2 D B1 B2 D BAC B1 B2 D
DD B1 B2 D B1 B2 D B1 B2 D S/G B1 B2 D
line_iom_smartLink.vsd
Figure 39 Data Delay between UPN and IOM 2.3.4.1 B1-, B2- and D-Channels
The lOM-interface B-channels are used to convey the two 64-kbit/s user channels in both directions. However, the SCOUT-P(X) only transfers the data transparently in the activated state (inc. analog loop activated) while the data are set to `1' in any non activated state. 2.3.4.2 Stop/Go Bit
The Stop/Go (S/G) bit can be controlled by the received UPN T-channel to transmit the state of the line card arbiter to the HDLC-controller of the terminal. If selected by the DIM2-0 bits ('0x1') in the MODEH register, the HDLC-transmitter evaluates the state of the S/G-bit before and during transmission of an HDLC-frame.
Data Sheet 65 2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.4.3 Available/Busy Bit
The A/B bit has been added to the IOM-2 frame for the operation of a S/T-terminal adapter based on the SBCX PEB 2081. It is used to transfer the state of the line card HDLC controller indicated by the UPN T-channel to the SBCX. If the A/B bit is '1', it indicates that the line card HDLC controller is available and Dchannel messages may be transmitted. If it changes to '0' the HDLC controller has to abort the transmission and has to restart the transmission after the A/B bit becomes '1' again. The A/B bit is used by the SBCX on a S/T interface option to control the ECHO channel of the S/T interface and the Stop/Go bit on the IOM-2 interface. 2.3.4.4 T-Bit Transfer
The layer-1 (UPN) part of the SCOUT-P(X) conveys the T-bit position of the UPN interface to either the S/G-bit position or the A/B-bit position according to the TCM bit in the TR_CONF0 register. The bit polarities are as follows: Downstream (UPN IOM) T-to A/B-mapping (TCM = '1'): T = 0: T = 1: T-to S/G-mapping (TCM = '0'): T = 0: T = 1: Upstream (IOM UPN) The T-channel in upstream direction is controlled by the BAC-bit of the IOM-2 interface. The T-channel transmits the inverse of the BAC-bit. Special care is taken so that the slave terminal will only send one HDLC-frame until the TlC-bus of the master IOM-2 interface is released. This is achieved by a circuitry which latches the BAC-state of `1' until at least one T-bit has been transmitted with the value of `0' which releases the TlC-bus of the master IOM-2 interface. BAC to T-mapping: BAC = 1 BAC = 0 T=0 T=1 no D-channel request D-channel request A/B = 1 S/G = 1 blocked A/B = 1 S/G = 0 available A/B = 0 S/G = 1 blocked A/B = 1 S/G = 1 available
Data Sheet
66
2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.5 Control of UPN
The layer-1 activation/deactivation can be controlled by an internal state machine via the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the default state the internal layer-1 state machine of the SCOUT-P(X) is used. To disable the internal state machine TR_CONF0.L1SW must be set to '1' and a C/I code TIM ('0000') has to be programmed into CIX0.CODX0 If the internal state machine is disabled the layer-1 commands, which are normally generated by the internal state machine can be written directly into the TR_CMD register or indications read out of the TR_STA register. The SCOUT-P(X) layer-1 control flow is shown in figure 40.
Disable internal Statemachine (TR_CONF.L1SW)
CIX0
C/I Command C/I Indication Layer-1 State Machine
CIR0
Transmit Command Register INFO Transmitter for Transmitter (TR_CMD) Receive Status Register INFO of Receiver Receiver (TR_STA)
Register
Layer-1 Control
Microcontroller Interface
layer1_ctl.vsd
Figure 40 Layer-1 Control 2.3.5.1 Internal Layer-1 Statemachine
In the following sections the layer-1 control by the SCOUT-P(X) state machine will be described. For the description of the IOM-2 C/I0 channel see also chapter 2.2.5. The layer-1 functions are controlled by commands issued via the CIX0 register. These commands, sent over the IOM C/I channel 0 to layer 1, trigger certain procedures, such as activation/deactivation, switching of test loops and transmission of special pulse patterns. These are governed by a layer-1 state machine which agrees with the activation/deactivation procedures as implemented in the SmartLink-P PSB 2197 or ISAC-P TE PSB 2196 respectively. Responses from layer 1 are obtained by reading the CIR0 register after a CIC interrupt (ISTA).
Data Sheet 67 2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.5.1.1 State Transition Diagram The state machine includes all information relevant to the user. The state diagram notation is given in figure 41. The informations contained in the state diagrams are: - State name - UPN signal transmitted (INFO) (see chapter 2.3.5.1.7) - C/I code received (commands) (see chapter 2.3.5.1.3) - C/I code transmitted (indications) (see chapter 2.3.5.1.6) - Transition criteria The transition criteria is grouped into: - C/I commands (see chapter 2.3.5.1.3) - Received infos on UPN (see chapter 2.3.5.1.4) - Reset (see chapter 2.3.5.1.5)
OUT
IN
IOM-2 Interface C/I code
Ind. Cmd. State
Unconditional Transition
UPN Interface INFO
ix
ir
statem_notation.vsd
Figure 41 State Diagram Notation The following example illustrates the use of a state diagram with an extract of the state diagram. The state explained is "Deactivated". The state may be entered: - from states "Power-Up", "Pending Deactivation", "Pending Activation", "Loop3" and the unconditional states "Reset" and "Test Mode i" after the C/I command "DI" has been received. The following informations are transmitted: - INFO 0 (no signal) is sent on the UPN interface. - C/I message "DC" is issued on the IOM-2 interface. The state may be left by either of the following methods: - Leave for the state "Power up" after synchronous or asynchronous "TIM" code has been received on IOM. - Leave for state "Pending Activation" in case C/I = AR is received.
Data Sheet 68 2001-03-07
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Interfaces - Leave for the state "Level Detect" after a signal different to 'INFO 0' has been recognized on the UPN interface. - Leave for the state "Loop 3" in case C/I = ARL is received. As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A "" stands for a logical AND combination. And a "+" indicates a logical OR combination. The sections following the state diagram contain detailed information about all states and signals used. Figure 42 shows the state transition diagram of the SCOUT-P(X) state machine. Figure 43 shows this for the state Loop 3.
Data Sheet
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Interfaces
DC ARL
DI TIM
DI TIM
SCP TMA SSP Test Mode i iti *
Deactivated i0 AR i0 i0
ARL Loop 3 3)
DI TIM
SCP SSP
AR DI TIM AR DI
PU
AR
PU
TIM
Pending Activation i1w i0 i0 DI RSY AR Level Detect i0 i0 i2 AR1) DI ARL2 AR Synchronized i1 i2 i2 i4
Power-Up i0 i0 i0
i0*TO1
ix DI
DR RES Reset i0 * TIM
DI*TO2 AI1) DI AIL2 AR Activated i3 i4 ix DR AR TIM*TO2
1)Indication
RESET2)
Pending Deactivation i0 i0
2)
Commands initiating unconditional transitions: RES, SSP, SCP TO1: 2 ms TO2: 1 ms
3)
depends on received S bit: S='0': AR or AI respectively S='1': ARL2 or AIL2 respectively Possible Reset sources: C/I command RESET, software reset SRES.RES_TR or reset from pin RST Loop 3 see next figure
statem_te_upn.vsd
Figure 42 State Transition Diagram
Data Sheet 70 2001-03-07
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Interfaces
ARL
AR TIM DI
PU
ARL
Pend. Loop 3 i1 i0 i1
AR TIM DI
ARL ARL i1*i3 Loop 3 Synchronized i3 i1 i3
AR TIM DI
RSY ARL Loop 3 Activated i3 i3
statem_te_aloop_upn.vsd
i3
Figure 43 State Transition Diagram of the Loop 3 State
Data Sheet 71 2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.5.1.2 States Reset, Pending Deactivation State after reset or deactivation from the UPN interface by info 0. Note that no activation from the terminal side is possible starting from this state. A `DI'-command has to be issued to enter the state 'Deactivated'. Deactivated The UPN interface is deactivated and the IOM-2 interface is or will be deactivated. Activation is possible from the UPN interface and from the IOM-2 interface. Power-Up The UPN interface is deactivated and the IOM-2 interface is activated, i.e. the clocks are running. Pending Activation Upon the command Activation Request (AR) the SCOUT-P(X) transmits the 2-kHz info 1w towards the network, waiting for info 2. Level Detect During the first period of receiving info 2 or under severe disturbances on the line the UPN receiver recognizes the receipt of a signal but is not (yet) synchronized. Synchronized The UPN receiver is synchronized and detects info 2. It continues the activation procedure by transmission of info 1. Activated The UPN receiver is synchronized and detects info 4. It concludes the activation procedure by transmission of info 3. All user channels are now conveyed transparently. Analog Loop 3 Pending Upon the C/l-command Activation Request Loop (ARL) the SCOUT-P(X) loops back the transmitter to the receiver and activates by transmission of info 1. The receiver is not yet synchronized. Analog Loop 3 Synchronized After synchronization the transmitter continues by transmitting info 3.
Data Sheet
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Interfaces Analog Loop 3 Activated After recognition of the looped back info 3 the channels are looped back transparently. Test Mode i After entering test mode initiated by SCP-, SSP-commands. Level Detect, Resynchronization During the first period of receiving info 2 or under severe disturbances on the line the UPN receiver recognizes the receipt of a signal but is not (yet) synchronized. In extremely rare situations of severe line disturbances, the UPN receiver might become locked in this state. To avoid this, it is recommended that the software issues an RES command to restart activation if SCOUT-P(X) remains in this state longer than an acceptable period. This timeout period should be at least 110 ms, but the exact period should be chosen by the user based on system concerns. Loop 2 The states for loop 2 are identical to the states of the regular TE operation. The loop 2 indications are output if the S-bit of the UPN frame is `1'.
State Synchronized Activated Reset state
S-bit = 0 AR AI
S-bit = 1 ARL2 AIL2
A software reset (RES) forces the SCOUT-P(X) to an idle state where INFO 0 is transmitted. Thus activation from the NT is not possible. Clocks are still supplied.
Data Sheet
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Interfaces 2.3.5.1.3 C/I Commands Command (Upstream) Timing Reset Send Single Pulses Send Continuous Pulses Activate Request Activate Request Loop 3 Deactivation Indication Abbr. Code Remarks TIM RES SSP SCP AR ARL Dl 0000 0001 0010 0011 1000 1001 1111 Local analog loop Layer-2 device requires clocks to be activated Statemachine reset AMI coded pulses transmitted at 4 kHz AMI coded pulses transmitted continuously
2.3.5.1.4 Receive Infos on UPN (Downstream) Name Info 0 Info 2 Abbr. Description i0 i2 No signal on the line 4-kHz burst signal F000100010001000100010101010001011111M1) DC2) Code violation in the framing bit 4-kHz burst signal No code violation in the framing bit User data in B-, D- and M-channels B-channels scrambled, DC-bit2) optional Any signal except info 2 or info 4
Info 4
i4
Info X Note:
1)
ix
The M-channel superframe is as follows: S-bits transparent T-bits set to '1' CV generated (see figure 37) DC-balancing bit
74 2001-03-07
2)
Data Sheet
PSB 21391 PSB 21393
Interfaces 2.3.5.1.5 Reset RES A low signal on the RST pin or setting the RES_TR bit in the SRES register to '1' resets also the layer-1 statemachine. The reset signals should be applied for a minimum of 2 DCL clock cycles. The function of these reset events is identical to the C/I code RES concerning the state machine.
2.3.5.1.6 C/I Indications Indication (Downstream) Deactivation Request Power-Up Test Mode Acknowledge Resynchronization Activation Request Activation Request Loop 3 Activation Request Loop 2 Activation Indication Abbr. Code Remarks DR PU TMA RSY AR ARL 0000 0111 0010 0100 1000 1001 Acknowledge for both SSP and SCP Receiver not synchronous Receiver synchronized Local loop synchronized Remote loop synchronized
ARL2 1010 AI 1100 1101 1110 1111
Activation Indication Loop 3 AIL Activation Indication Loop 2 AIL2 Deactivation Confirmation DC
Local loop activated Remote loop activated Line- and if MODE1.CFS = '1' also lOMinterface are powered down
Data Sheet
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Interfaces 2.3.5.1.7 Transmit Infos on UPN (Upstream)
I
Name Info 0 Info 1w
Abbr. Description i0 i1w No signal on the line Asynchronous wake signal 2-kHz burst rate F0001000100010001000101010100010111111 Code violation in the framing bit 4-kHz burst signal F000100010001000100010101010001011111M1) DC2) Code violation in the framing bit 4-kHz burst signal No code violation in the framing bit User data in B-, D- and M-channels B-channels scrambled, DC-bit2) optional Half-bauded AMI-coded pulses are transmitted continuously One half-bauded AMI-coded pulse is transmitted in each UPN frame
Info 1
i1
Info 3
i3
Test Info 1 it1 Test Info 2 it2
1)
The M-channel superframe is as follows: S-bits set to '0' T-bits set to '1' CV generated (see figure 37) DC-balancing bit
2)
Data Sheet
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Interfaces 2.3.5.1.8 Example of Activation/Deactivation An example of an activation/deactivation of the UPN interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown in figure 44.
C Interface SPU=0, CFS=1
IOM-2 Interface (C/I) DC DI
TE
UPN Interface INFO 0
LT
IOM-2 Interface (C/I) DC DI
SPU=1 PU SPU=0 AR RSY T1 AR INFO 1W INFO 2 INFO 0 INFO 1 INFO 4 T2 AI INFO 3 T2 AI UAI AR
INFO 0 T3 DR DI DC INFO 0 INFO 0 T3
DR
DI DC
T1: < 10 ms time for synchronization T2: 1 ms time for detecting INFO3/4 T3: 2 ms time for error free detection of INFO 0
act_deac_te_int_upn.vsd
Figure 44 Example of Activation/Deactivation Initiated by the Terminal (TE). Activation/Deactivation under control of the internal layer-1 statemachine
Data Sheet
77
2001-03-07
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Interfaces 2.3.5.2 External Layer-1 Statemachine
Instead of using the integrated layer-1 statemachine it is also possible to implement the layer-1 statemachine completely in software. The internal layer-1 statemachine can be disabled by setting the L1SW bit in the TR_CONF0 register (see chapter 7.1.1) to '1'. The transmitter is completely under control of the microcontroller via register TR_CMD (see chapter 7.1.5). The status of the receiver is stored in register TR_STA (see chapter 7.1.4) and has to be evaluated by the microcontroller. This register is updated continuously. If not masked a RIC interrupt (see chapter 7.1.6) is generated by any change of the register contents. The interrupt is cleared after a read access to this register.
Data Sheet
78
2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.5.2.1 Activation initiated by the Terminal (TE, SCOUT-P(X)) INFO 1W has to be transmitted as long as INFO 0 is received. INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 1 or INFO 3 respectively has to be started.
C Interface TE UPN Interface INFO 0 XINF='001' RINF='01' XINF='000' RINF='10' XINF='010' INFO 1 INFO 4 RINF='11' XINF='011' T2 TE INFO 3 T1 TE INFO 1W INFO 2 INFO 0 LT
INFO 0 RINF='00' XINF='000' T3 TE INFO 0 INFO 0
T1 TE: 4 to 12 UPN frames T2 TE: 4 UPN frames 4 UPN frames T3 TE:
act_deac_te-ext_upn.vsd
Figure 45 Example of Activation/Deactivation initiated by the Terminal (TE). Activation/Deactivation completely under software control
Data Sheet
79
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Interfaces 2.3.5.2.2 Activation initiated by the Line Termination LT INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 1 or INFO 3 respectively has to be started.
C Interface TE UPN Interface INFO 0 RINF='01' T1TE RINF='10' XINF='010' INFO 1 INFO 4 RINF='11' XINF='011' T2TE INFO 3 INFO 2 LT
INFO 0 RINF='00' XINF='000' T3TE INFO 0 INFO 0
T1TE: 4 to 12 UPN frames 4 UPN frames T2TE: T3TE: 4 UPN frames
act_deac_lt_ext_upn.vsd
Figure 46 Example of Activation/Deactivation initiated by the Line termination (LT). Activation/Deactivation completely under software control
Data Sheet
80
2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.6 Level Detection Power Down
If MODE1.CFS is set to '0', the clocks are also provided in power down state, whereas if CFS is set to '1' only the analog level detector is active in power down state. All clocks, including the IOM interface, are stopped. The data lines and the FSC are 'high', whereas DCL is 'low' and BCL is 'high'. An activation initiated from the exchange side (Info 2 on UPN detected) will have the consequence that clock signals are provided automatically if the bit LDD of register TR_CONF0 is set to '0'. From the terminal side an activation must be started by setting and resetting the SPUbit in the IOM_CR register and writing TIM to the CIX0 register or by resetting MODE1.CFS=0. 2.3.7 Transceiver Enable/Disable
The layer-1 part of the SCOUT-P(X) can be enabled/disabled by configuration with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX . By default all layer-1 functions are enabled (DIS_TR = '0', DIS_TX = '0'). If DIS_TX = '1' only the transmit buffers are disabled. The receiver will monitor for incoming calls in this configuration. If DIS_TR = '1' all layer-1 functions are disabled including the level detection circuit of the receiver. In this case the power consumption of the Layer-1 is reduced to a minimum. The HDLC controller and codec part can still operate via IOM-2. The DCL and FSC pins become inputs.
Data Sheet
81
2001-03-07
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Interfaces 2.3.8 Test Functions
The SCOUT-P(X) provides several test and diagnostic functions for the transceiver: 2.3.8.1 UPN Transceiver Test
Two test loops allow the local or the remote test of the transceiver function. - The local loop (test loop 3) which is activated by a C/I0 ARL command loops the transmit data of the transmitter to its receiver. The information of the IOM-2 upstream B- and D-channels is looped back to the downstream B- and D-channels. The T-bit is also transparent which means that the state of the BAC-bit is looped back to the S/Gor A/B-bit. - The remote loop (test loop 2) is activated by the UPN interface and loops the received data back to the UPN interface. The D-channel information received from the line card is transparently forwarded to the downstream IOM-2 D-channel. The downstream B-channel information on IOM-2 is fixed to `FF'H while test loop 2 is active. Additional to C/I0 a remote loop (loop 2) is indicated by the RLP bit in the TR_STA register. 2.3.8.2 Test Signals on the UPN Interface
Two kinds of test signals may be sent by the SCOUT-P(X): - The single pulses are of alternating polarity at 2kHz (one pulse per UPN frame). The corresponding C/I command is SSP (Send single pulses). - The continuous pulses are pulses of alternating polarity. The corresponding C/I command is SCP (Send continuous pulses).
Data Sheet
82
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Interfaces 2.3.9 Transmitter Characteristics
The half-bauded pseudo-ternary pulse shaping is achieved with the integrated line driver which drives a binary 'High' via typical 30 output impedance at a line current of 40mA. The line driver circuitry is designed to lower the EMI radiation and therefore reducing the expense for external EMC circuitry. The simplified equivalent circuit of the transmitter is shown in figure 47.
VDDL open VSSL
'+1' '0' '-1'
Zi LIa
'+1' '0' '-1' Level
'+1' '0' '-1' trans_stage_upn.vsd
TR_CONF2.DIS_TX
VSSL open VDDL
Zi LIb
Figure 47 Equivalent Internal Circuit of the Transmitter Stage
Data Sheet
83
2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.10 Receiver Characteristics
The SCOUT-P(X) covers the electrical requirements of the UPN interface for loop lengths of up to 4.5 kft on AWG 24 cable and 1.0 km on J-Y(ST) Y 2 x 2 x 0.6 cable. The receiver consists of a differential input stage, a peak detector and a set of comparators. A simplified equivalent circuit of the receiver is shown in figure 48.
Figure 48 Equivalent Internal Circuit of the Receiver Stage The data detection threshold Vref of the peak detector is continuously adapted to the line level. The peak detector requires maximum 2 s to reach the peak value while storing the peak level for at least 250 s (RC > 1 ms). The additional level detector for power up/down control works with a fixed threshold voltage VrefLD. The level detector monitors the line input signals to detect whether an INFO is present. In order to additionally reduce the bit error rate in severe conditions, the SCOUT-P(X) performs oversampling of the received signal and uses majority decision logic. The receive signal is sampled at 15.36MHz clock intervals (XTAL).
Data Sheet
84
2001-03-07
PSB 21391 PSB 21393
Interfaces 2.3.11 UPN Interface Circuitry
Using a 3.3V power supply a 1:1 transformer has to be connected to the 2 wire UPN interface. Using a 5V power supply a 2:1 transformer has to be used. Therefore the TRS bit in the TR_CONF2 register has to be set to '1'. The connection of the line transformer is shown in figure 49. External to the line interface pins Lla and Llb a transformer and external resistors are connected as shown. Note that the internal resistors of the transformer are calculated as zero. The actual values of the external resistors must take into account the real resistor of the chosen transformer.
Transformer Ratio 2:1 5V Supply Voltage 40 2:1
U PN
LIa 160 SCOUT-P(X)
100nF 330nF 160 LIb 40
Transformer Ratio 1:1 3.3V Supply Voltage 10 1:1
U PN
LIa
SCOUT-P(X)
50 100nF 330nF 50 LIb 10
UPNTRAN.DRW
Figure 49 Connection of the Line Transformers and Power Supply to the SCOUT-P(X)
Data Sheet
85
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3 HDLC Controller
The HDLC controller handles layer-2 functions of the D- channel protocol (LAPD) or Bchannel protocols. It can access the D or B-channels or any combination of them e.g. 18 bit IDSL data (2B+D) by setting the enable HDLC channel bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register. It performs the framing functions used in HDLC based communication: flag generation/ recognition, bit stuffing, CRC check and address recognition. One 64 byte FIFO for the receive and one for the transmit direction are available. They are implemented as cyclic buffers. The transceiver reads and writes data sequentially with constant data rate whereas the data transfer between FIFO and microcontroller uses a block oriented protocol with variable block sizes. The configuration, control and status bits related to the HDLC controller are all assigned to the address range 20H-29H. (see chapter 7). 3.1 Message Transfer Modes
The HDLC controller can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus the receive data flow and the address recognition features can be programmed in a flexible way to satisfy different system requirements. The structure of a LAPD two-byte address is shown below. High Address Byte SAPI1, 2, SAPG C/R 0 Low Address Byte TEI 1, 2, TEIG EA
For the address recognition the HDLC controller contains four programmable registers for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values for the "group" SAPI (SAPG = 'FE' or 'FC') and TEI (TEIG = 'FF'). The received C/R bit is excluded from the address comparison. EA is the address field extension bit which is set to '1' for LAPD protocol. There are 5 different operating modes which can be selected via the mode selection bits MDS2-0 in the MODEH register:
Data Sheet
86
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.1.1 Non-Auto Mode (MDS2-0 = '01x')
Full address recognition with one-byte (MDS = '010') or two-byte (MDS = '011') address comparison All frames with valid addresses are accepted and the bytes following the address are transferred to the P via RFIFO. 3.1.2 Transparent Mode 0 (MDS2-0 = '110'). no address recognition
Characteristics:
Characteristics:
Every received frame is stored in RFIFO (first byte after opening flag to CRC field). 3.1.3 Transparent Mode 1 (MDS2-0 = '111'). SAPI recognition
Characteristics:
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and "group" SAPI (FEH/FCH). In the case of a match, all following bytes are stored in RFIFO. 3.1.4 Transparent Mode 2 (MDS2-0 = '101'). TEI recognition
Characteristics:
A comparison is performed only on the second byte after the opening flag, with TEI1, TEI2 and group TEI (FFH). In case of a match the rest of the frame is stored in the RFIFO. 3.1.5 Extended Transparent Mode (MDS2-0 = '100'). fully transparent
Characteristics:
In extended transparent mode fully transparent data transmission/reception without HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/ check, bitstuffing mechanism. This allows user specific protocol variations. Also refer to chapter 3.5.
Data Sheet
87
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.2 3.2.1 3.2.1.1 Data Reception Structure and Control of the Receive FIFO General Description
The 64-byte cyclic RFIFO buffer has variable FIFO block sizes (thresholds) of 4, 8, 16 or 32 bytes which can be selected by setting the corresponding RFBS bits in the EXMR register. The variable block size allows an optimized HDLC processing concerning frame length, I/O throughput and interrupt load. The transfer protocol between HDLC FIFO and microcontroller is block orientated with the microcontroller as master. The control of the data transfer between the CPU and the HDLC controller is handled via interrupts (HDLC controller Host) and commands (Host HDLC controller). There are three different interrupt indications in the ISTAH register concerned with the reception of data: - RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length (EXMR.RFBS) can be read from RFIFO. The message which is currently received exceeds the block size so further blocks will be received to complete the message. - RME (Receive Message End) interrupt, indicating that the reception of one message is completed, i.e. either * a short message is received (message length the defined block size (EXMR.RFBS) or * the last part of a long message is received (message length > the defined block size (EXMR.RFBS)) and is stored in the RFIFO. - RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not be stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the host fails to respond quickly enough to RPF/RME interrupts since previous data was not read by the host. There are two control commands (bits of CMDR) that are used with the reception of data: - RMC (Receive Message Complete) command, telling the HDLC controller that a data block has been read from the RFIFO and the corresponding FIFO space can be released for new receive data. - RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the receive FIFO of any data (e.g. used before start of reception). It has to be used after having changed the mode.
Data Sheet
88
2001-03-07
PSB 21391 PSB 21393
HDLC Controller The following description of the receive FIFIO operation is illustrated in figure 50 for a RFIFO block size (threshold) of 16 and 32 bytes. The RFIFO requests service from the microcontroller by setting a bit in the ISTAH register, which causes an interrupt (RPF, RME, RFO). The microcontroller then reads status information (RBCH,RBCL), data from the RFIFO and changes the RFIFO block size (EXMR.RFBS). A block transfer is completed by the microcontroller via a receive message complete (CMDR.RMC) command. This causes the space of the transferred bytes being released for new data and in case the frame was complete (RME) the reset of the receive byte counter RBC (RBCH,RBCL). The total length of the frame is contained in the RBCH and RBCL registers (RBC11...0). If a frame is longer than 4095 bytes, the RBCH.OV (overflow) bit will be set. The least significant bits of RBCL contain the number of valid bytes in the last data block indicated by RME (length of last data block selected block size). Table 7 shows which RBC bits contain the number of bytes in the last data block or number of complete data blocks respectively. If the number of bytes in the last data block is '0' the length of the last received block is equal to the block size. Table 7 Receive Byte Count with RBC11...0 in the RBCH and RBCL registers EXMR.RFBS bits '00' '01' '10' '11' Selected block size 32 byte 16 byte 8 byte 4 byte Number of complete data blocks in RBC11...5 RBC11...4 RBC11...3 RBC11...2 bytes in the last data block in RBC4...0 RBC3...0 RBC2...0 RBC1...0
The transfer block size (EXMR.RFBS) is 32 bytes by default. If it is necessary to react to an incoming frame within the first few bytes the microcontroller can set the RFIFO block size to a smaller value. Each time a CMDR.RMC or CMDR.RRES command is issued, the RFIFO access controller sets its block size to the value specified in EXMR.RFBS, so the microcontroller has to write the new value for RFBS before the RMC command. When setting an initial value for RFBS before the first HDLC activities, a RRES command must be issued afterwards. The RFIFO can hold any number of frames fitting in the 64 bytes. At the end of a frame, the RSTA byte is always appended. All generated interrupts are inserted together with all additional information into a wait line to be individually passed to the host. For example if several data blocks have been received to be read by the host and the host acknowledges the current block, a new RPF or RME interrupt from the wait line is immediately generated to indicate new data.
Data Sheet 89 2001-03-07
PSB 21391 PSB 21393
HDLC Controller
RAM EXMR.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo an receive pool full interrupt ISTAH.RPF is set. The P has read the 4 bytes, sets RFBS=01 (16 bytes) and completes the block transfer by an CMDR.RMC command. Following CMDR.RMC the 4 bytes of the last block are deleted.
RAM
32 RFACC
32 RFACC
RFIFO ACCESS CONTROLLER 16 RFBS=11 8
RFIFO ACCESS CONTROLLER 16 RFBS=01 8 4
HDLC Receiver RFIFO
4 HDLC Receiver RPF EXMR.RFBS=01 RMC
P
RAM HDLC Receiver
RSTA
RBC=4h
RAM
32 RFACC HDLC Receiver
RSTA
32 RFACC
The HDLC receiver has written further data into the FIFO. When a frame is complete, a status byte (RSTA) is appended. Meanwhile two more short frames have been received.
RFIFO ACCESS
RSTA RSTA
RFIFO ACCESS 16 CONTROLLER RFBS=01 8
RSTA RSTA
16
CONTROLLER RFBS=01
8
RBC=14h
RBC=16h P
RFIFO
RFIFO
FIFO.
RMC
P When the RFACC detects 16 valid bytes, it sets an RPF interrupt. The P reads the 16 bytes and acknowledges the transfer by setting CMDR.RMC. This causes the space occupied by the 16 bytes being released.
After the RMC acknowledgement the RFACC detects an RSTA byte, i.e. end of the frame, therefore it asserts an RME interupt and increments the RBC counter by 2.
Figure 50 RFIFO Operation
Data Sheet
90
RME
RPF
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.2.1.2 Possible Error Conditions during Reception of Frames
If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTA byte will be set. If a complete frame is lost, i.e. if the FIFO is full when a new frame is received, the receiver will assert a Receive Frame Overflow (RFO) interrupt. The microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it reads the same data again and again. On the other hand, if it doesn't read or doesn't want to read all data, they are deleted anyway after the RMC command. If the microcontroller reads data without a prior RME or RPF interrupt, the read data is undefined but the content of the RFIFO would not be corrupted.
Data Sheet
91
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.2.1.3 Data Reception Procedure
The general procedures for a data reception sequence are outlined in the flow diagram in figure 51.
START
Receive Message End RME ? N Receive Pool Full RPF ? Y Read Counter RD_Count := RFBS or RD_Count := RBC
Y
N
Read RBC RD_Count := RBC
1)
Read RD_Count bytes from RFIFO
*
Change Block Size Write EXMR.RFBS (optional)
Receive Message Complete Write RMC
RBC = RBCH + RBCL register RFBS: Refer to EXMR register
1) *
In case of RME the last byte in RFIFO contains the receive status information RSTA
HDLC_Rflow.vsd
Figure 51 Data Reception Procedures
Data Sheet
92
2001-03-07
PSB 21391 PSB 21393
HDLC Controller Figure 52 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) is received. The FIFO threshold (block size) is set to 32 byte (EXMR.RFBS = '00') in this example: * After 32 bytes of frame 1 have been received an RPF interrupt is generated to indicate that a data block can be read from the RFIFO. * The host reads the first data block from RFIFO and acknowledges the reception by RMC. Meanwhile the second data block is received and stored in RFIFO. * The second 32 byte block is indicated by RPF which is read and acknowledged by the host as described before. * The reception of the remaining 4 bytes plus RSTA are indicated by RME. * The host gets the number of received bytes (COUNT = 5) from RBCL/RBCH and reads out the RFIFO. The frame is acknowledged by RMC. * The second frame is received and indicated by RME interrupt. * The host gets the number of bytes (COUNT = 13) from RBCL/RBCH and reads out the RFIFO. The RFIFO is acknowledged by RMC. * The third frame is transferred in the same way.
IOM Interface
Receive Frame 32 68 Bytes 32 4 12 12 Bytes Bytes 12 12
RD 32 Bytes RPF
RD 32 Bytes
RD RD Count 5 Bytes
1) *
RD RD Count 13 Bytes
1) *
RD RD Count 13 Bytes
1) *
RMC RPF
RMC RME
RMC RME
RMC RME
RMC
CPU Interface
1) *
The last byte contains the receive status information
fifoseq_rec.vsd
Figure 52 Reception Sequence, Example
Data Sheet
93
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.2.2 Receive Frame Structure
The management of the received HDLC frames as affected by the different operating modes (see chapter 3.1) is shown in figure 53.
FLAG
H9T! H9T H9T HP9@
ADDR
699S@TT
CTRL
8PIUSPG
I
96U6
CRC
TU6UVT
FLAG
I

6
% T6Q T6Q! T6QB

U@D U@D! U@DB

SADAP
STU6
I

6' U@D U@D!

SADAP
STU6

UhhrAA

SADAP
STU6
UhhrAA

T6Q T6Q! T6QB

SADAP
STU6
UhhrAA!

U@D U@D! U@DB

SADAP
STU6
9rpvvAsATiy)

8S8AvhyyArqAvASADAPAvsA@YHSS8S8A2A
8hrqAvuASrtvr

6qqrAvhyyArqAvASADAPAvsA@YHSTS6A2A
TrqAvAADAPSrtvr

ThAsAurA8yAAvryqAvA8hrAsAhA'A7vA6qqr
fifoflow_rec.vsd
Figure 53 Receive Data Flow
Data Sheet
94
2001-03-07
PSB 21391 PSB 21393
HDLC Controller The HDLC controller indicates to the host that a new data block can be read from the RFIFO by means of an RPF interrupt (see previous chapter). User data is stored in the RFIFO and information about the received frame is available in the RSTA, RBCL and RBCH registers which are listed in table 8. Table 8 Receive Information at RME Interrupt Information Type of frame (Command/ Response) Recognition of SAPI Location RFIFO (last byte) RFIFO (last byte) RFIFO (last byte) RFIFO (last byte) RFIFO (last byte) RFIFO (last byte) Bit C/R Mode Non-auto mode, 2-byte address field Transparent mode 1 Non-auto mode, 2-byte address field Transparent mode 1 All except transparent mode 0 All All All All All All All
SA1, 0
Recognition of TEI Result of CRC check (correct/incorrect) Valid Frame Abort condition detected (yes/no)
TA CRC VFR RAB RDO RBC4-0 RBC11-0 OV
Data overflow during reception of RFIFO a frame (yes/no) (last byte) Number of bytes received in RFIFO Message length RFIFO Overflow RBCL Reg. RBCL Reg. RBCH Reg. RBCH Reg.
Data Sheet
95
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.3 3.3.1 3.3.1.1 Data Transmission Structure and Control of the Transmit FIFO General Description
The 64-byte cyclic XFIFO buffer has variable FIFO block sizes (thresholds) of 16 or 32 bytes, selectable by the XFBS bit in the EXMR register. There are three different interrupt indications in the ISTAH register concerned with the transmission of data: - XPR (Transmit Pool Ready) interrupt, indicating that a data block of up to 16 or 32 byte (block size selected via EXMR:XFBS) can be written to the XFIFO. An XPR interrupt is generated either * after an XRES (Transmitter Reset) command (which is issued for example for frame abort) or * when a data block from the XFIFO is transmitted and the corresponding FIFO space is released to accept further data from the host. - XDU (Transmit Data Underrun) interrupt, indicating that the transmission of the current frame has been aborted (seven consecutive '1's are transmitted) as the XFIFO holds no further transmit data. This occurs if the host fails to respond to an XPR interrupt quickly enough. - XMR (Transmit Message Repeat) interrupt, indicating that the transmission of the complete last frame has to be repeated as a collision on the S bus has been detected and the XFIFO does not hold the first data bytes of the frame (collision after the 16th or 32nd byte of the frame, respectively). Three different control commands are used for transmission of data: - XTF (Transmit Transparent Frame) command, telling the HDLC controller that up to 16 or 32 byte (according to selected block size) have been written to the XFIFO and should be transmitted. A start flag is generated automatically. - XME (Transmit Message End) command, telling the HDLC controller that the last data block written to the XFIFO completes the corresponding frame and should be transmitted. This implies that according to the selected mode a frame end (CRC + closing flag) is generated and appended to the frame. - XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the transmit FIFO of any data. Optionally two additional status conditions can be read by the host: - XDOV (Transmit Data Overflow), indicating that the data block size has been exceeded, i.e. more than 16 or 32 byte were entered and data was overwritten. - XFW (Transmit FIFO Write Enable), indicating that data can be written to the XFIFO. This status flag may be polled instead of or in addition to XPR.
Data Sheet 96 2001-03-07
PSB 21391 PSB 21393
HDLC Controller The XFIFO requests service from the microcontroller by setting a bit in the ISTAH register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read the status register STAR (XFW, XDOV), write data in the FIFO and it can change the transmit FIFO block size (EXMR.XFBS) if required. The instant of the initiation of a transmit pool ready (XPR) interrupt after different transmit control commands is listed in table 9.
Table 9 XPR Interrupt (availability of the XFIFO) after XTF, XME Commands CMDR. XTF XTF & XME XME Transmit pool ready (XPR) interrupt initiated... as soon as the selected buffer size in the FIFO is available after the successful transmission of the closing flag. The transmitter sends always an abort sequence as soon as the selected buffer size in the FIFO is available, two consecutive frames share flags
When setting XME the transmitter appends the FCS and the end flag at the end of the frame. When XTF & XME has been set, the XFIFO is locked until successful transmission of the current frame, so a consecutive XPR interrupt also indicates successful transmission of the frame whereas after XME or XTF the XPR interrupt is asserted as soon as there is space for one data block in the XFIFO. The transfer block size is 32 bytes by default, but sometimes, if the microcontroller has a high computational load, it is useful to increase the maximum reaction time for an XPR interrupt. The maximum reaction time is: tmax = (XFIFO size - XFBS) / data transmission rate A selected block size of 16 bytes means that an XPR interrupt is indicated when there are still 48 bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes block size the XPR is initiated when there are still 32 bytes (64 bytes - 32 bytes), i.e. the maximum reaction time for the smaller block size is 50 % higher with the trade-off of a doubled interrupt load. A selected block size of 32 or 16 bytes respectively always indicates the available space in the XFIFO. So any number of bytes smaller than the selected XFBS may be stored in the FIFO during one "write block" access cycle. Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next XTF,XME or XRES command. XRES resets the XFIFO. The XFIFO can hold any number of frames fitting in the 64 bytes.
Data Sheet
97
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.3.1.2 Possible Error Conditions during Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly enough to an XPR interrupt, an XDU (transmit data underrun) interrupt will be raised. If the HDLC channel becomes unavailable during transmission the transmitter tries to repeat the current frame as specified in the LAPD protocol. This is impossible after the first data block has been sent (16 or 32 bytes), in this case an XMR transmit message repeat interrupt is set and the microcontroller has to send the whole frame again. Both XMR and XDU interrupts cause a reset of the XFIFO. The XFIFO is locked while an XMR or XDU interrupt is pending, i.e. all write actions of the microcontroller will be ignored as long as the microcontroller has not read the ISTAH register with the set XDU, XMR interrupts. If the microcontroller writes more data than allowed (16 or 32 bytes), then the data in the XFIFO will be corrupted and the STAR.XDOV bit is set. If this happens, the microcontroller has to abort the transmission by CMDR.XRES and to restart.
Data Sheet
98
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.3.1.3 Data Transmission Procedure
The general procedures for a data transmission sequence are outlined in the flow diagram in figure 54.
START
N
Transmit Pool Ready XPR ? Y
Command XTF
Write Data (up to 32 Bytes) to XFIFO
N
End of Message ? Y Command XTF+XME
End
HDLC_Tflow.vsd
Figure 54 Data Transmission Procedure
Data Sheet
99
2001-03-07
PSB 21391 PSB 21393
HDLC Controller The following description gives an example for the transmission of a 76 byte frame with a selected block size of 32 byte (EXMR:XFBS=0): * The host writes 32 bytes to the XFIFO, issues an XTF command and waits for an XPR interrupt in order to continue with entering data. * The HDLC controller immediately issues an XPR interrupt (as remaining XFIFO space is not used) and starts transmission. * Due to the XPR interrupt the host writes the next 32 bytes to the XFIFO, followed by the XTF command, and waits for XPR. * As soon as the last byte of the first block is transmitted, the HDLC controller issues an XPR interrupt (XFIFO space of first data block is free again) and continues transmitting the second block. * The host writes the remaining 12 bytes of the frame to the XFIFO and issues the XTF command together with XME to indicate that this is the end of frame. * After the last byte of the frame has been transmitted the HDLC controller releases an XPR interrupt and the host may proceed with transmission of a new frame.
IOM Interface
Transmit Frame 32 76 Bytes 32 12
WR 32 Bytes
WR 32 Bytes XTF XPR XTF
WR 12 Bytes XPR XTF+XME XPR
CPU Interface
fifoseq_tran.vsd
Figure 55 Transmission Sequence, Example
Data Sheet
100
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.3.2 Transmit Frame Structure
The transmission of transparent frames (XTF command) is shown in figure 56. For transparent frames, the whole frame including address and control field must be written to the XFIFO. The host configures whether the CRC is generated and appended to the frame (default) or not (selected in EXMR.XCRC). Furthermore, the host selects the interframe time fill signal which is transmitted between HDLC frames (EXMR:ITF). One option is to send continuous flags ('01111110'), however if D-channel access handling is required, the signal must be set to idle (continuous '1's are transmitted).
FLAG
ADDR
699S@TT
CTRL
8PIUSPG
I
96U6
CRC
8C@8FS6H

FLAG
UhvAUhhrAAhr YUA
YADAP

UurA8S8AvAtrrhrqAiAqrshy
fifoflow_tran.vsd
DsA@YHSY8S8AvArAA8S8AvAhrqrq
Figure 56 Transmit Data Flow 3.4 Access to IOM Channels
By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register the HDLC controller can access the D, B1, B2 channels or the combination of them (e.g. 18 bit IDSL data (2B+D)). In all modes sending works always frame aligned, i.e. it starts with the first selected channel whereas reception looks for a flag anywhere in the serial data stream.
Data Sheet
101
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.5 Extended Transparent Mode
This non-HDLC mode is selected by setting MODE2...0 to '100'. In extended transparent mode fully transparent data transmission/reception without HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism. This allows user specific protocol variations. 3.5.1 Transmitter
The transmitter sends the data out of the FIFO without manipulation. Transmission is always IOM-frame aligned and byte aligned, i.e. transmission starts in the first selected channel (B1, B2, D, according to the setting of register HCI_CR in the IOM Handler) of the next IOM frame. The FIFO indications and commands are the same as in other modes. If the microcontroller sets XTF & XME the transmitter responds with an XPR interrupt after sending the last byte, then it returns to its idle state (sending continuous `1'). If the collision detection is enabled (MODE.DIM = '0x1') the stop go bit (S/G) can be used as clear to send indication as in any other mode. If the S/G bit is set to '1' (stop) during transmission the transmitter responds always with an XMR (transmit message repeat) interrupt. If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs out of data then it will assert an XDU (transmit data underrun) interrupt. 3.5.2 Receiver
The reception is IOM-frame aligned and byte aligned, like transmission, i.e. reception starts in the first selected channel (B1, B2, D, according to the setting of register HCI_CR in the IOM Handler) of the next IOM frame. The FIFO indications and commands are the same as in others modes. All incoming data bytes are stored in the RFIFO and additionally made available in RSTA.
Data Sheet
102
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.6 HDLC Controller Interrupts
The cause of an interrupt related to the HDLC controller is indicated by the HDLC bit in the ISTA register. This bit points at the different interrupt sources of the HDLC controller part in the ISTAH register. The individual interrupt sources of the HDLC controller during reception and transmission of data are explained in chapter 3.2.1 or 3.3.1 respectively. MASK ST CIC TIN WOV TRAN MOS HDLC ISTA ST CIC TIN WOV TRAN MOS HDLC MASKH RME RPF RFO XPR XMR XDU ISTAH RME RPF RFO XPR XMR XDU
INT Figure 57 Interrupt Status Registers of the HDLC Controller Each interrupt source in ISTAH register can be selectively masked by setting to "1" the corresponding bit in MASKH.
Data Sheet
103
2001-03-07
PSB 21391 PSB 21393
HDLC Controller 3.7 Test Functions
The following test and diagnostic functions for the D-channel are available: - Digital loop via TLP (Test Loop, TMH register) command bit (figure 58): The TX path of layer 2 is internally connected with the RX path of layer 2. The output from layer 1 on DD is ignored. This is used for testing layer 2 functionality excluding layer 1 (loopback between XFIFO and RFIFO). - Test of layer-2 functions while disabling all layer-1 functions and pins associated with them (including clocking) via bit TR_CONF0.DIS_TR. The HDLC controller and codec part can still operate via IOM-2. DCL and FSC pins become input.
Figure 58 Layer 2 Test Loops
Data Sheet
104
2001-03-07
PSB 21391 PSB 21393
Codec 4 Codec
The codec bridges the gap between the audio world of microphones, earphones, loudspeakers and the PCM digital world by providing a full PCM codec with all the necessary transmit and receive filters. Because the requirements for the codec correspond to the ARCOFI-SP PSB 2163 or ARCOFI(R)-BA PSB 2161 respectively the architecture, functionality and transmission characteristics are similar to those devices. A block diagram of the codec is shown in figure 59. The codec can be subdivided into three main blocks: * Analog Front End (AFE) * Digital Signal Processor (DSP) * Codec Digital Interface (CDI) A detailed description can be found in the following chapters.
AFE
VREF BGREF AXI MIP1 MIN1 MIP2 MIN2 AINMUX AMI A/D Dec Dec VREF
DSP
Frequency Correction Filter Data Source Selection, Voice Data Manipulation (Coding, Masking, Conferencing)
CDI
CH1X C010X C011X CH2X C020X C021X
Digital Gain Adjustment Speakerphone Function Tone Generator Int Sidetone
Codec Voice Data
IOM-2 Handler
LSP LSN
ALS
CH2R C020R C021R CH1R C010R C011R
D/A HOP HON AHO
Int
Control/ config. Data
C Interface or Monitor Handler
codec_arch.vsd
Figure 59 Architecture of the codec
Data Sheet
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Codec The controlling and programming of the various operation modes, configurations and coefficients can be done via the microcontroller interface or the IOM-2 monitor channel and is described in the corresponding interface section. An overview on these programmable parameters can be found in chapter 4.8. 4.1 Analog Front End (AFE) Description
The Analog Front End section of the codec is the interface between the analog transducers and the digital signal processor. In the transmit direction the AFE function is to amplify the transducer input signals (microphones) and to convert them into digital signals. In the AFE receive section the incoming digital signal is converted to an analog signal which is output to an earpiece and/or a loudspeaker. The three AFE configuration registers (ACR, ATCR, ARCR) provide a high flexibility to accommodate an extensive set of user procedures and terminal attributes. Figure 60 shows the block diagram of the Analog Front End: .
DREF
Figure 60 Block Diagram of AFE
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Codec Two differential inputs (MIP1/MIN1 and MIP2/MIN2) and one single-ended input (AXI) can be connected to the amplifier AMI via an analog input multiplexer (ATCR.AIMX). The programmable amplifier AMI (ATCR.MIC) provides a coarse gain adjustment range from 0...42dB in 6dB steps. The maximum value of the programmable gain adjustment of the microphone amplifier with specified transmission characteristics is 36dB for the differential input. The maximum gain value with specified transmission characteristics of the single ended input AXI is 24dB. Fine gain adjustment is performed in the digital domain via the programmable gain adjustment stage GX (see signal processor section). This allows a perfect level adaptation to various types of microphone transducers without loss in the signal to noise performance. The fully differential output HOP/HON connects the amplifier AHO to a handset earpiece. Differential output LSP/LSN is provided for use with a 50 (5V supply voltage) or 25 (3.3V supply voltage) respectively loudspeaker. The programmable amplifiers AHO and ALS (ARCR.HOC, ARCR.LSC) provide a coarse gain adjustment range from 11.5dB...21.5dB (ALS) or 2.5dB...-21.5dB (AHO) respectively. The step size is for both amplifiers 3dB. Fine gain adjustment is performed in the digital domain via the programmable adjustment stage GR. Each output of the differential amplifiers AHO and ALS can be powered down separately (ACR.DHOP, DHON, DLSP, DLSN). By setting ACR.SEM, a powered down loudspeaker output can be grounded internally for a single ended operation. The bandgap reference voltage is low-pass filtered via a capacity connected to pin BGREF. The internal and external reference voltages are derived from this filtered bandgap reference voltage providing a good noise performance. A square wave signal from the tone generator can be output directly to the loudspeaker amplifier (TGSR.TRL) via a level shifter. Note: The single-ended input (AXI) is internally connected to VREF. To avoid an unsymmetric input signal to the internal amplifer module, external resitors must not be connected between AXI and GND or AXI and VREF. 4.1.1 AFE Attenuation Plan
Figure 61 shows the attenuation plan of the AFE for the transmit and receive direction. The levels are given for the digital reference level (0dBm0) and the max. PCM level in A-law coding (3.14dBm0) at the two supply voltages 3.3V and 5V. The stated microphone amplifier gain is the maximum gain for guaranteed transmission characteristics. In the receive path the stated loudspeaker or handset output amplification is the maximum selectable gain at the maximum digital PCM level (3.14dBm0) for guaranteed transmission characteristics.
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Codec
.
Figure 61 AFE Attenuation Plan
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Codec 4.2 Signal Processor (DSP) Description
The signal processor (DSP) has been conceived to perform all ITU-T and ETSI (NET33) recommended filtering in transmit and receive paths and is therefore fully compatible to the ITU-T G.712 and ETSI (NET33) specifications. The data processed by the DSP is provided in the transmit direction by an oversampling A/D-converter situated in the analog front end (AFE). Once processed, the speech signal is converted into an 8-bit Alaw or -law PCM format or remains as a 16-bit linear word (2s complement) if the compression stage is bypassed. In the receive direction, the incoming PCM data is expanded into a linear format (if the linear mode is selected, the expansion logic is bypassed) and subsequently processed until it is passed to the oversampling D/Aconverter. Additionally to these standard codec functions an universal tone generation unit and a high quality speakerphone function (only SCOUT-PX) is provided. Figure 62 shows the processor signal flow graph which illustrates the following description of the signal processing in receive and transmit direction, the tone generation and speakerphone function.
Data Sheet
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DLP2
SC SD SC
-Law CH20R 8-bit LIN MAS K2
T RR GR DHPR DHPR
1
CH2R 16-bit LIN
CH21R
A-Law
INT
1 0...-6 dB FR MAAR PGCR AGCR
LP
GR
GHR
FR AGCR
HPR
R DAT 1
idle
-Law MAS K1 8-bit LIN
CH1R
CH10R CH11R 16-bit LIN
E RA
R eceive DS S R
us er programmable
C o d e c V o i c e D a ta
16-bit LIN AT T 2R AT T 1R Voice Data Manipulation 1 1
0...- dB
A-Law
DLP1
to I O M - H a n d le r
Data Sheet
CME SP S PS T Speakerphone support FX GX SCOUT-PX only DS S 1X MAS Kx MPx DS S 2X DF xX DF xR
T rans mit
FX GX
AGCX DT MF DHPX A-Law E NX1 CH1X CH10X CH11X MAS K1 8-bit LIN 1 XDAT 6...0 dB DHPX idle -L aw
DL S
DT MF
DE C
HPX GHX
1 16-bit LIN 1 1
LP AGCX
DT MF -
1
1
Figure 62 Processor Signal Flow Graph
LP
A-Law idle -L aw MAS K2 SC 0 1 PGZ 8-bit LIN 1 CH21X S C,S D E NX2 CH2X CH20X
1
T RX
DT MF
T one Generator S peakerphone

AF E
S upport GZ
GZ
DT MF
110
to ALS ampl.
s quare
s quare
trapezoid
s ine
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Codec 4.2.1 Transmit Signal Processing
In the transmit direction a series of decimation filters reduces the sampling rate down to the 8-kHz PCM-rate. These filters attenuate the out-of-band noise by limiting the transmit signal to the voice band. The decimation stages end with a low-pass filter (LP). If the tone generation unit is connected to the transmit direction (TGSR.DTMF = '1'), a special 2-kHz DTMF low-pass filter is placed in the transmit path. This filter guarantees an attenuation of all unwanted frequency components, if DTMF signals are transmitted. Additionally, it is possible to add a programmable tone signal to the transmit voice signal (TGSR.TRX = '1'). The GX-gain adjustment stage is digitally programmable allowing the gain to be programmed from + 6 to 0 dB in steps of 0.25 dB (values from - dB to 12 dB are programmable but the transmission characteristics are only guaranteed in a specific range, see table 10 and 11). Two bytes are necessary to set GX to the desired value. After reset, the GX-gain stage is bypassed. The transmit path contains a programmable high performance frequency response correction filter FX allowing an optimum adaptation to different types of microphones (dynamic, piezoelectric or electret). Twelve bytes are necessary to set FX to the desired frequency correction function. After reset, the FX-frequency correction filter is bypassed. Figure 63 shows the architecture of the FX/FR-filter. A high-pass filter (HPX) is also provided to remove unwanted DC components. In the voice data manipulation block a data format selection (A-law, -law, 8-bit linear, 16 bit linear), the masking of the 8-bit data and the data source selection for the two data channels at the interface to the IOM handler is realized. 4.2.2 Receive Signal Processing
The incoming data from the IOM handler is similar to transmit direction processed by the VDM block. A programmable sidetone gain stage GZ adds a sidetone signal to the incoming voice signal. The sidetone gain can be programmed from - 54 to 0 dB within a 1 dB tolerance range (values from - dB to 12 dB are programmable but the transmission characteristics are only guaranteed in a specific range, see table 10 and 11). Respectively two bytes are coded in the CRAM to set GZ to the desired value. After reset, the GZ-gain stage is disabled (- dB). A high-pass filter (HPR) is also provided to remove disturbances from 0 to 50/60 Hz due to the telecommunication network. The frequency response correction filter (FR) is similar to the FX-filter allowing an optimum adaptation to different types of loudspeakers or earpieces. Twelve bytes are necessary to set FR to the desired frequency correction function. After reset, the FR-frequency correction filter is bypassed.
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Codec The GR-gain adjustment stage is digitally programmable from - 6 to 0 dB in steps 0.25 dB (- dB and others are also possible). Respectively two bytes are coded in the CRAM to set GR to the desired value. After reset, the GR-gain stage is bypassed. A low-pass filter limits the signal bandwidth in the receive direction according to ITU-T and ETSI (NET33) recommendations. A series of low-pass interpolation filters increases the sampling frequency up to the desired value. The last interpolator feeds the D/A-converter.
Equalizer 1
Equalizer 2
High- / Low- Pass
ITD02288
Figure 63 Architecture of the FX- and FR-Correction Filter
Data Sheet
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Codec 4.2.3 Programmable Coefficients for Transmit and Receive
This section gives a short overview of important programmable coefficients. For more detailed information a coefficient software package is available (SCOUT MASTER SIPO 21383). Table 10 Description of the programmable Level Adjustment Parameters Parameter GX GR GZ # of CRAM Bytes 2 2 2 Range Comment
12 to - dB Transmit gain adjustment 6 to 0 dB Transmission characteristics guaranteed 12 to - dB Receive gain adjustment 0 to -6 dB Transmission characteristics guaranteed 12 to - dB Sidetone gain adjustment
Table 11 Subset of Coefficients for GX, GR and GZ: Gain [dB] 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 MSB 10H 10H 10H 01H 20H 30H 13H B0H A0H 23H 22H 23H 32H B1H B1H 33H B2H B3H LSB 01H 31H 13H 4BH 94H 94H 51H 39H 49H 01H B4H 12H A4H BCH 03H 39H 5AH 49H Gain [dB] 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -7.0 -8.0 -9.0 -10.0 -11.0 MSB A0H B3H A3H A2H BBH BBH BAH BAH A2H AAH 9BH AAH AAH B9H 9AH 9BH 9BH 93H LSB 01H 42H 2BH 32H 4AH 13H 29H 5BH 01H 1BH 3AH 33H 22H 2CH BCH 13H 32H 02H Gain [dB] -12.0 -13.0 -14.0 -15.0 -16.0 -17.0 -18.0 -19.0 -20.0 -21.0 -22.0 -23.0 -24.0 -25.0 -26.0 - MSB A9H 9CH 99H 8CH 82H 84H 89H 8BH 84H 8CH 82H 84H 89H 8BH 84H 88H LSB 01H 51H 13H 1BH 7BH 4BH 6AH 0CH 1CH 1CH 7CH 4CH 6BH 0DH 1DH 01H
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Codec 4.3 Tone Generation
The ASP contains a universal tone generator which can be used for tone alerting, call progress tones, DTMF-signals or other audible feedback tones. All the tone generation configurations are programmable in the registers TGCR (Tone Generator Configuration Register) and TGSR (Tone Generator Switch Register) and the CRAM parameters. The tone generation unit consists of following main blocks: * Four Signal Generators * Sequence Generator * Control Generator * Tone Filter * Tone Level Adjustment Figure 64 shows the signal flow graph of the tone generation unit and illustrates the following functional description. 4.3.1 Four Signal Generators
The four signal generators can be programmed by CRAM parameters in frequency (Fn,FD) and gain (Gn,GDn). For the signal generators F1,F2,F3 a trapezoid or square waveform can be selected by setting the TGCR.SQTR bit. The signal generator FD has a trapezoid waveform. The signal generators in conjunction with the tone sequence generator and the control generator allow to generate different multitone patterns without reprogramming the necessary parameters. 4.3.2 Sequence Generator
The sequence generator can be enabled or disabled by setting the TGCR.SEQ (Sequence Generator) bit. If the sequence generator is enabled depending on the TGCR.TM (Tone Mode) bit two or three tone sequences of the signals (F1, G1), (F2,G2) and (F3,G3) are generated. The CRAM parameters T1, T2, T3 determine the duration of these individual signals. If the sequence generator is disabled a continuous tone is generated. The selected signal generator depends on the TGCR.TM (Tone Mode) bit. By setting the TGSR.DT (Dual Tone Mode) bit the output of the signal generator FD (FD, GDn) can be added to the tone signal which is determined by the SEQ and TM bit. Note: The dual tone mode and the three tone sequence can only be used if the DTMF mode is disabled (TGSR.DTMF = '0') Table 12 shows the programmable CRAM Parameters of the tone and sequence generator. In Table 13 possible tone signals are listed which can be realized with the control bits SEQ, TM and DT.
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T one Generator PT T one R es et Control T one to ALS ampl. via T R L s witch Generator T ON, T OF F S equence Generator T 1, T 2, T 3 ET
Data Sheet
SM TM S EQ T1 T one Level T2 E qualiz ET T3 F DT 1 T one 1 ET F er n GT X to T R X s witch S aturatio Adjus t. 1 T one F ilter ( A1, A2, K, GE ) to T R R GT R s witch 1 T rans mit DT MF 1 T ONGE N.D RW 1 DT MF
S QT R
S ignal Generator
F 1, G1
s quare/
trapezoid
S ignal Generator
F 2, G2
s quare/
trapezoid
DT MF
Figure 64 Signal Flow Graph of the Tone Generation Unit Codec
115
S ignal Generator
F 3, G3
s quare/
trapezoid
S ignal Generator
GD3
F D,
GD2
trapezoid
GD1
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Table 12 CRAM Parameters of the Signal and Sequence Generator Parameter Fn Gn Tn FD GDn # of CRAM Bytes 2/2/2 1/1/1 2/2/2 2 1/1/1 Range 50 Hz to 4 kHz 16 kHz/m; (m 3) 0 dB to - 48 dB 10 ms to 8 s 50 Hz to 4 kHz 0 dB to - 48 dB Comment Trapezoid shaped tone Square-wave signal Gain adjustment for square/trapezoid generator Period of time for two- or threetone sequences Trapezoid shaped tone Gain adjustment for trapezoid generator
n is either 1, 2 or 3 Note: 0-dB gain setting of G1, G2 or G3 and GD1, GD2 or GD3 corresponds to the maximum PCM-level (A-Law: + 3.14 dBm0) Table 13 Tone Generation SEQ TM DT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Generated tone Continuous signal Continuous signal Continuous signal Continuous signal tone sequence tone sequence tone sequence tone sequence [F1, G1] [F1, G1] + [FD, GD1] [F2, G2] [F2, G2] + [FD, GD2] [F1, G1, T1] / [F2, G2, T2] [(F1, G1) + (FD, GD1), T1)] / [(F2, G2) + (FD, GD2), T2)] (F1, G1, T1) / (F2, G2, T2) / (F3, G3, T3) [(F1, G1) + (FD, GD1), T1] / [(F2, G2) + (FD, GD2), T2] / [(F3, G3) + (FD, GD3), T3]
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Codec 4.3.3 Control Generator
Controlling of the generated tone follows the setting of the control bits ET (Enable Tone) and PT (Pulsed Tone) and the CRAM parameters TON and TOFF corresponding table 14 and table 15. Table 14 Control Generator ET 0 0 1 1 PT 0 1 0 1 Generator Output No tone the tone is pulsed with the programmable parameters TON, TOFF continuous tone generation without breaks the tone is pulsed with the programmable parameters TON, TOFF
Table 15 CRAM Parameters of the Control Generator Parameter TON TOFF # of CRAM Bytes 2 2 Range 20 ms to 16 min 20 ms to 16 min Comment Period while the tone generator is turned on Period while the tone generator is turned off
Four typical examples for the control generator programming are shown in Figure 65. In the automatic stop mode (TGCR.SM = '1') the selected tone sequence is only stopped after a sequence is completed. This avoids unpleasant sounds when stopping the tone generator. The tone signal can be fed directly to the input of the loudspeaker amplifier by setting the TGSR.TRL bit to '1'. In this mode only a square wave (fixed amplitude of VDD) is available from the signal generators (F1, F2, F3)and the TGCR.SQTR bit has no effect.
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Codec
Figure 65 Typical Control Generator Applications 4.3.4 Tone Filter
A programmable tone filter can be switched in the tone signal path by setting the ETF (Enable Tone Filter) bit. The tone filter contains a programmable equalizer and a saturation amplifier (see figure 64). A generated square-wave or trapezoid signal can be converted by the equalizer into a sine-wave signal. The equalizer is realized as a band-pass filter.
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Codec The filter parameters (center frequency, bandwidth and attenuation of the stop-band) are programmable by the CRAM parameters listed in Table 16 Table 16 CRAM Parameters of the Tone Filter Parameter A1 A2 # of CRAM Bytes 1 1 Range 200 Hz to 4 kHz 0 to - 1 Comment Center frequency Determines with A1 and K the bandwidth. The closer A2 comes to -1, the smaller the bandwidth. Attenuation of the stop-band Saturation amplification
K GE
1 1
0 to 54 dB + 12 to - 12 dB
A maximum attenuation of the first harmonic frequency of 50 dB is possible. Figure 66 shall illustrate the equalizer parameters.
Figure 66 Filter Parameters of the Equalizer
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Codec The two main purposes of the programmable saturation amplification are: * Level balancing of the filtered signal (avoidance of overload effects). * Amplification up to + 12 dB followed by a saturation (3.14 dBm0) of the incoming signal. This saturation amplification converts a sine-wave signal into a square-wave or a trapezoid signal where their edges are eliminated. This method produces pleasant ringing tones. 4.3.5 Tone Level Adjustment
The generated tone signal can be amplified separate for transmit and receive direction with the gain parameters GTX, GTR and switched to the transmit/receive channels by setting TGSR.TRX (Tone Ringing Transmit) and TRR (Tone Ringing Receive). Table 17 CRAM Parameters of the Tone Level Adjustment Parameter GTX # of CRAM Bytes 1 Range 0 dB to - 50 dB (also - dB) 0 dB to - 50 dB (also - dB) Comment Level adjustment in transmit direction
GTR
1
Level adjustment in receive direction
4.3.6
DTMF Mode
The DTMF mode of the tone generator is selected by setting the TGSR.DTMF to '1'. The trapezoid output signal of the signal generators (F3, G3) and (FD, GD3) are added and fed in the transmit path. The CRAM parameters for the DTMF signals are listed in table 18 In the DTMF mode a special DTMF filter is switched to the transmit channel. Undesirable frequency components are filtered by this special DTMF-low-pass filter to the following limits: Frequency Band 0 - 300 Hz 300 - 3400 Hz 3400 - 4000 Hz Min. Attenuation 33 dB 20 dB 33 dB
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Codec The pre-emphasis of 2 dB between the high and the low DTMF-frequency groups has to be set with the independent gain parameters (G3 and GD3 resp.) of the trapezoid generators. All generated DTMF-frequencies are guaranteed within a 1 % deviation. Table 18 DTMF-frequency (F3,FD) Programming ITU-T Q.23 [Hz] Low Group 697 770 852 941 High Group 1209 1336 1477 1633 SCOUT Nominal [Hz] 697.1 770.3 852.2 941.4 1209.5 1336.9 1477.7 1632.8 Relative Deviation from ITU-T + 143 ppm + 390 ppm + 235 ppm + 425 ppm + 414 ppm + 674 ppm + 474 ppm - 122 ppm Coefficients high [HEX] 4F A6 45 20 B4 C8 49 40 low [HEX] 16 18 1B 1E 26 2A 2F 34
Note: The deviations due to the inaccuracy of the incoming clock DCL/MCLK, when added to the nominal deviations tabulated above give the total absolute deviation from the CCITT-recommended frequencies
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Codec 4.4 Speakerphone Support
The speakerphone option of the SCOUT-PX performs all functions required for echo suppression without any external components, just by software. All these operational functions realized by the signal processor are completely parameterized. This technique offers a high level of flexibility and reproducibility. Basically, three static mode of operation can be distinguished: "transmit mode", "receive mode", and "idle mode". In the speech mode the receive path is attenuated while in listen mode the attenuation is switched to the transmit path. In the idle mode the attenuation is halved between transmit and receive paths. The amount of switchable attenuation can be chosen by software. The speakerphone goes into transmit mode if both, the speech detector and the speech comparator SCAE, indicate the presence of a speech signal in the transmit direction that is strong enough. Switching into receive mode appears if the speech comparator SCLE and the speech detector in the receive path both detect a speech signal that is strong enough. If no speech is detected at all, the speakerphone goes into idle mode. As the signal flow graph of the speakerphone option shows (see figure 67), the complete operational algorithm is situated between the analog front end/signal processing and the compression/expansion logic. Thus telephone sets can be optimized and adjusted to the particular physical and acoustic environment. The main features of the speakerphone signal processing are: * Two separate attenuation stages activated by voice, one for the transmit and one for the receive path. They are controlled by the current and past speech activities. * Immediate mode switching mainly controlled by two comparators, one at the acoustic side and one at the line side. Capable of handling very long echo times. * All parameters can be adjusted independently and are closely related to the physical phenomenons. * Speech detection by special speech detectors in the respective transmit and receive directions. Different time constants are separately programmable for signal and noise. * Background noise monitoring to eliminate continuous background noise from speech control. All time constants are user programmable.
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Codec
Signal-Processing & Analog Front End
AGCX
GHX
COMP SX PCM
SX SD
Attenuation SCAE Control SCLE
SD
Signal-Processing & Analog Front End
SR
GR GHR
SR AGCR
EXP PCM
Figure 67 Speakerphone Signal Flow Graph of the SCOUT-PX 4.4.1 Attenuation Control Unit
The Attenuation Control unit controls the attenuation stages GHX of the transmit and GHR of the receive directions respectively. The programmable loss is switched either completely to a single path or, in the "IDLE" mode, is halved to each direction. In addition, attenuation is also influenced by the Automatic Gain Control stages (AGCX and AGCR). In order to keep the total loop gain always constant, the sweep range (of ATT) is automatically enlarged with high-gain amplification of the AGCs while it will be accordingly reduced with low-gain. Changing from one speakerphone mode into another one depends on the determinations of one comparator plus the corresponding speech detector. Hence attenuation is influenced by the current and past speech activities. Also rate of change varies: changing from "transmit mode" or "receive mode" to "idle mode" is programmable by the rate factor DS. Direct changes from "transmit mode" to "receive mode" or viceversa and changes from "idle mode" to "transmit mode" or "receive mode" can be programmed via the factor SW in a large range.
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Codec Description of the programmable parameters: Parameter TW ATT # of CRAM Bytes 1 1 Range 16 ms to 4 s 0 dB to 95 dB Comment
DS SW 4.4.2
1 1
Wait time Attenuation programmed in GHR or GHX if speech activity for the other side was detected 0.6 to 680 ms/dB Decay Speed (Decay Time TD = DS x ATT/2) 0.0052 to 10 ms/dB Switching time (dependent on ATT)
Speakerphone Test Function and Self Adaption
For optimizing the speakerphone performance the SCOUT-PX provides following test functions: - The two register bits (XCSR.SPST) indicate the different speakerphone states (receive, transmit and idle). - The momentary magnitude of the AGC attenuation in receive direction can be read out by an SOP_D command. 4.4.3 Speech Detector
The speech detectors (see figure 68) contained in both transmit and receive directions consist of two main blocks: * Background Noise Monitor (BNM) * Signal Processing Although the speech detector is fully parameterized, the standard coefficient set for the speech detector fits perfectly to almost every application and normally don't have to be altered.
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Codec
Figure 68 Speech Detector Signal Flow Graph 4.4.3.1 Background Noise Monitor
The tasks of the noise monitor are to differentiate voice signals from background noise, even if it exceeds the voice level, and to recognize voice signals without any delay. Therefore the background noise monitor consists of the low-pass filter 2 (LP2) and the offset in two separate branches. Basically it works on the burst-characteristic of the speech: voice signals consist of short peaks with high power (bursts). In contrast, background noise can be regarded approximately stationary from its average power. Low-pass filter 2 provides different time constants for noise (non-detected speech) and speech. It determines the average of the noise reference level. In case of background noise the level at the output of LP2 is approximately the level of the input. Due to the offset OFF the comparator remains in the initial state. In case of speech at the comparator input the difference between the signal levels of the offset branch and of the LP2-branch increases and the comparator changes state. At speech bursts the digital signals arriving at the comparator via the offset branch change faster than those via the LP2-branch so that the comparator changes its polarity. Hence two logical levels are generated: one for speech and one for noise.
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Codec A small fade constant (LP2N) enables fast settling down the LP2 to the average noise level after the end of speech recognition. However, a too small time constant for LP2N can cause rapid charging to such a high level that after recognizing speech the danger of an unwanted switching back to noise exists. It is recommended to choose a large rising constant (LP2S) so that speech itself charges the LP2 very slowly. Generally, it is not recommended to choose an infinite LP2S because then approaching the noise level is disabled. During continuous speech or tones the LP2 will be charged until the limitation LP2L is reached. Then the value of LP2 is frozen until a break discharges the LP2. This limitation LP2L of this charging especially on the RX-path permits transmission of continuous tones and "music on hold". The offset stage represents the exact level threshold in [dB] between the speech signal and averaged noise. 4.4.3.2 Signal Processing
As described in the preceding chapter, the background noise monitor is able to discriminate between speech and noise. In very short speech pauses e.g. between two words, however, it changes immediately to non-speech, which is equal to noise. Therefore a peak detection is required in front of the Noise Monitor. The main task of the Peak Detector is to bridge the very short speech pauses during a monologue so that this time constant has to be long. Furthermore, the speech bursts are stored so that a sure speech detection is guaranteed. But if no speech is recognized the noise low-pass LP2 must be charged rapidly to the average noise level. Additionally the noise edges are to be smoothed. Therefore two time constants are necessary and are separately programmable: PDS for speech and PDN for space (background noise) signals. The Peak Detector is very sensitive to spikes. The LP1 filters the incoming signal containing noise in a way that main spikes are eliminated. Due to the programmable time constant it is possible to refuse high-energy sibilants and noise edges. To compress the speech signals in their amplitudes and to ease the detection of speech, the signals have to be companded logarithmically. Hereby, the speech detector should not be influenced by the system noise which is always present but should discriminate between speech and background noise. The limitation of the logarithmic amplifier can be programmed via the parameter LIM, where the upper half-byte features LIMX and the lower half-byte LIMR. LIM is related to the maximum PCM level (+3.14 dBm0). A signal exceeding the limitation defined by LIM is getting amplified logarithmically, while very smooth system noise below is neglected. It should be the level of the minimum system noise which is always existing; in the transmit path the noise generated by the telephone circuitry itself and in receive direction the level of the first bit which is stable without any speech signal at the receive path.
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Codec Description of the programmable speech detector parameters: Parameter LP1 OFF PDS PDN LP2S LP2N LP2L LIMX, LIMR # of CRAM Bytes 1 1 1 1 1 1 1 1 Range 1 to 512 ms 0 to 50 dB 1 to 512 ms 1 to 512 ms 4 to 2000 ms 1 to 512 ms 0 to 95 dB - 36 to - 78 dB Comment Time constant LP1 Level offset up to detected noise Time constant PD (signal) Time constant PD (noise) Time constant LP2 (signal) Time constant LP2 (noise) Limitation of LP2, related to LIM Limitation of logarithmic amplifier
4.4.4
Speech Comparators (SC)
Switching from one active mode to another one is controlled by the speech comparators, provided the speech detectors are indicating speech. There are two speech comparators, one at the acoustic (AE) and one at the line side (LE). These comparators continuously compare the signal levels of both signal paths and control the effect of the echoes at the acoustic side and the line side. Once speech activity has been detected, the comparator switches at once in that direction in which the speech signal is stronger. For this purpose each signal is compared to the sum of the other and the returned echo.
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Codec 4.4.4.1 Speech Comparator at the Acoustic Side (SCAE)
In principle, the SCAE works according to the following equation: if SX > SR + VAE then TX else RX
Being in RX-mode, the speech comparator at the acoustic side controls the switching to TX-mode. Only if the SX-signal is higher than the SR-signal plus the expected/measured acoustic level enhancement (VAE), the comparator switches immediately to TX-mode. Physically the level enhancement (VAE) is divided into two parts: GAE and GDAE.
Figure 69 Speech Comparator at the Acoustic Side
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Codec At the SCAE-input, logarithmic amplifiers compress the signal range. Hence after the required signal processing for controlling the acoustic echo, pure logarithmic levels on both paths are compared. Principally, the main task of the comparator is to control the echo. The internal coupling due to the direct sound and mechanical resonances are covered by GAE. The external coupling, mainly caused by the acoustic feedback, is controlled by GDAE/PDAE. The Gain of the Acoustic Echo (GAE) corresponds to the terminal couplings of the complete telephone: GAE is the measured or calculated level enhancement between both receive and transmit inputs of the SCAE (see figure 67). It equals the sum of the amplification of ALS plus the gain due to the loudspeaker/microphone coupling plus the TX-amplification of AMIC1 and GX1. To succeed in a sure differentiation between original speech and echo, it must be guaranteed that the TX-signal does not run into saturation due to the loudspeaker/microphone coupling. Therefore, it is recommended to reduce the TX-gain by 10 dB in front of the SCAE at least in the loudest loudspeaker volume step. To fulfill the sending loudness rating, this gain is realized by the LGAX/ AGCX which follows the SCAE. Of course, the GAE has to be reduced by the same amount. To control the acoustic feedback two parameters are necessary: GDAE-features the actual reserve on the measured GAE. Together with the Peak Decrement (PDAE) it simulates the echo behaviour at the acoustic side: After RX-speech has ended there is a short time during which hard couplings through the mechanics and resonances and the direct echo are present. Till the end of that time (t) the level enhancement VAE must be at least equal to GAE to prevent clipping caused by these internal couplings. Then, only the acoustic feedback is present. This coupling, however, is reduced by air attenuation. For this in general the longer the delay, the smaller the echo being valid. This echo behaviour is featured by the decrement PDAE.
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Figure 70 Interdependence of GDAE and PDAE According to figure 70, a compromise between the reserve GDAE and the decrement PDAE has to be made: a smaller reserve (GDAE) above the level enhancement GAE requires a longer time to decrease (PDAE). It is easy to overshout the other side but the intercommunication is harder because after the end of the speech, the level of the estimated echo has to be exceeded. On the contrary, with a higher reserve (GDAE*) it is harder to overshout continuous speech or tones, but it enables a faster intercommunication because of a stronger decrement (PDAE*). Two pairs of coefficients, GDSAE/PDSAE when speech is detected, and GDNAE/ PDNAE in case of noise, offer a different echo handling for speech and non-speech. With speech, even if very strong resonances are present, the performance will not be worsened by the high GDSAE needed. Only when speech is detected, a high reserve prevents clipping. A time period ETAE [ms] after speech end, the parameters of the comparator are switched to the "noise" values. If both sets of the parameters are equal, ETAE has no function.
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Codec Description of the programmable parameters: Parameter GAE GDSAE PDSAE GDNAE PDNAE ETAE 4.4.4.2 # of CRAM Bytes 1 1 1 1 1 1 Range - 48 to + 48 dB 0 to 48 dB 0.16 to 42 ms/dB 0 to 48 dB 0.16 to 42 ms/dB 0 to 1020 ms Comment Gain of Acoustic Echo Reserve when speech is detected Peak Decrement when speech is detected Reserve when noise is detected Peak Decrement when noise is detected Echo time
Speech Comparator at the Line Side (SCLE)
Principally, the SCLE works similarly to the SCAE. The formula of SCLE is the following: if SR > SX + VLE then RX else TX
Being in TX-mode, the speech comparator at the line side controls the switching to RXmode. When the SR-signal is higher than the SX-signal plus the expected/measured echo return loss (VLE) and if SDR has detected speech, the comparator switches immediately to RX-mode.
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Figure 71 Speech Comparator at the Line Side The Gain of the Line Echo (GLE) directly corresponds to the echo return loss of the link. Generally, it is specified to 27 dB. However, the worst case loss can be estimated to 10 dB. This means, the echo returns at least attenuated by 10 dB. Similarly to the acoustic side, GDLE at the line side features the reserve above GLE which is necessary to control the echo via the decrement PDLE. GDLE and PDLE are interdependent. Exactly t [ms] after the end of RX-speech the level enhancement VLE must be at least GLE to prevent clipping. Two pairs of coefficients are available: GDSLE/PDSLE while speech is detected and GDNLE/PDNLE in case of noise. This offers the possibility to control separately the farend echo during speech and the near-end echo while noise is detected. However, this requires an attenuation between the speech detectors SDX and SDR: If the SDX does not recognize any speech, the SDR must not detect speech due to the far-end echo. Note, that LIMX and LIMR are also influencing the sensitivity of the speech detection. ETLE [ms] after the final speech detection the parameter sets are switched. If both sets are equal, ETLE has no meaning.
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Codec Description of the programmable parameters: Parameter GLE GDSLE PDSLE GDNLE PDNLE ETLE 4.4.4.3 # of CRAM Bytes 1 1 1 1 1 1 Range - 48 to + 48 dB 0 to 48 dB 0.16 to 42 ms/dB 0 to 48 dB 0.16 to 42 ms/dB 0 to 1020 ms Comment Gain of Line Echo Reserve when speech is detected Peak Decrement when speech is detected Reserve when noise is detected Peak Decrement when noise is detected Echo time
Automatic Gain Control of the Transmit Direction (AGCX)
Optionally an AGCX is inserted into the transmit path (see figure 72) to reach nearly constant loudness ratings independent from the varying distance between the speaking person and the microphone. The AGCX works only together with the speakerphone function (GCR.SP=1). Operation of the AGCX depends on a threshold level. The threshold is defined by the parameter COMX (value relative to the maximum PCM-value). Regulation follows two time constants: TMHX for signal amplitudes above the threshold and TMLX for amplitudes below. Usually TMHX will be chosen up to 10 times faster than TMLX. The bold line in figure 73 depicts the steady-state output level of the AGCX as a function of the input level.
Figure 72 Block Diagram of the AGC in Transmit Direction
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Codec For reasons of physiological acceptance the AGCX gain is automatically reduced in case of continuous background noise e.g. by ventilators. The reduction is programmed via the NOlSX-parameter. When the noise level increases the threshold determined by NOISX, the amplification will be reduced by the same amount the noise level is above the threshold. A programmable Loudness Gain Adjustment stage (LGAX) offers the possibility to amplify the transmit signal after the speech detector SDX. If a lower signal range in front of the SDX is necessary to determine between speech and echo a part of the transmit signal amplification can be transferred to the LGAX. It is enabled with the bit GCR.SP. Note: Even if the AGCX is disabled in speakerphone mode the LGAX remains enabled. If the speakerphone is in receive mode, the AGCX is not working; instead the last gain setting is used and regulation starts with this value as soon as the speakerphone returns into transmit mode again. For transmission measurements with this transient behavior it is recommended not to use a continuous sine wave signals but some kind of synthetic speech (e.g. switched noise or Composite Source Signal CSS). The sweep range of the switchable attenuation ATT (see chapter 4.4.1) is affected by the AGCX. If the automatic gain control enlarges the signal level, the sweep range will be increased accordingly in order to obtain a constant over-all gain in transmit and receive direction (constant TCL, constant echo return loss). The initial gain (AGIX) is used immediately after enabling the AGCX to allow a fast settling time of the AGC.
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AGC INPUT LEVEL
-50dBm0 -40dBm0 -30dBm0 -20dBm0 -10dBm0
MAX. PCM
MAX. PCM
AGX=0...+18dB
-10dBm0
AGC OUTPUT LEVEL AGX+|AAX|
-20dBm0
COMX
-30dBm0
AGX
-40dBm0
-50dBm0 XKEN.DRW
Figure 73 Level Diagram For the AGC in Transmit Direction
Description of the programmable parameters: Parameter # of CRAM Bytes LGAX COMX AAX AGX AGIX TMLX TMHX NOISX 1 1 1 1 1 1 1 1 Range - 12 to 12 dB 0 to - 73 dB 0 to 47 dB 0 to 18 dB 0 to 18 dB 1 to 2700 ms/dB 1 to 340 ms/dB 0 to - 95 dB Comment Loudness Gain Adjustment Compare level rel. to max. PCM-value Attenuation range of Automatic Control Gain range of Automatic control Initial AGC gain transmit Settling time constant for lower levels Settling time constant for higher levels Threshold for AGC-reduction by background noise
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Codec 4.4.5 Automatic Gain Control of the Receive Direction (AGCR)
The Automatic Gain Control of the receive direction AGCR (see figure 74) is similar to the transmit AGC. One additional parameter (AAR) offers more flexibility since the AGCR is able to attenuate signals as well. Depending on the parameters AAR and AGR different behaviours of the AGCR are possible as figure 75 illustrates. For example with AGR set to 0dB and AAR set to maximum (-48 dB) the AGCR acts as a limiter. The AGCR is working only together with the speakerphone function (GCR.SP=1). The digital gain stage LGAR is always enabled in speakerphone mode, independent of the setting of GCR.AGCR. It is highly recommended to program reasonable amplifications in the digital gain stages. Otherwise the ASP will run into saturation above the 3.14 dB PCM-value. Note that the speech detector for the receive direction is supplied with the signal that comes out of the AGR-block unless XCR.PGCR = '1'.
Figure 74 Function of the Receive AGC
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AGC INPUT LEVEL
-50dBm0 -40dBm0 -30dBm0 -20dBm0 -10dBm0 MAX. PCM MAX. PCM
AGR=0...+18dB AAR=0...-48dB AGR+|AAR|
-10dBm0
AGC OUTPUT LEVEL
-20dBm0
COMR
-30dBm0
AGR>0
AGR=0
-40dBm0
-50dBm0
RKEN.DRW
Figure 75 Level Diagram For the AGC in Receive Direction If the speakerphone is in transmit mode, the AGCR is not working; instead the last gain setting is used and the regulation starts with this value when the speakerphone has gone back into receive mode again. The initial attenuation (AGIR) is used immediately after enabling the AGCR to allow a fast settling time of the AGC. The sweep range of the switchable attenuation ATT is affected by the AGCR. If the automatic gain control enlarges or reduces the signal level, the sweep range will be adjusted automatically in a way, that the over-all gain in transmit and receive direction remains constant (constant TCL, constant echo return loss). Because of this the AGCR can be used for a comfortable receive volume control where the TCL value is the same for each volume setting and thus providing an optimal speakerphone performance. For such a volume control the momentary attenuation of the AGCR has to be read out by a SOP_D command. The parameters AGIR, COMR, can be determined for the desired volume change and written back in the CRAM.
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Codec Description of the programmable parameters: Parameter # of CRAM Bytes LGAR COMR AAR AGIR AGR TMLR TMHR NOISR 1 1 1 1 1 1 1 1 Range - 12 to 12 dB 0 to - 73 dB 0 to - 47 dB 18 to - 47 dB 0 to 18 dB 1 to 2700 ms/dB 1 to 340 ms/dB 0 to - 95 dB Comment Loudspeaker Gain Adjustment Compare level re. to max. PCM-value Attenuation range of Automatic control Initial AGC attenuation/ gain receive Gain range of Automatic control Settling time constant for lower levels Settling time constant for higher levels Threshold for AGC-reduction by background noise
4.4.6
Speakerphone Coefficient Set
Table 19 shows a possible configuration for a speakerphone application and can be used as a basic programming set. Table 19 Basic Coefficient Set CMD Sequence COP_A COP_A COP_A COP_A COP_A COP_A COP_A COP_A COP_B COP_B COP_B COP_B COP_B COP_B COP_B COP_B Coefficient GAE GLE ATT ETAE ETLE TW DS SW GDSAE PDSAE GDNAE PDNAE GDSLE PDSLE GDNLE PDNLE Code 0EH E5H 48H 0CH 32H 09H 25H 64H 20H 05H 20H 05H 40H 02H 40H 02H Value 5.3 dB - 10.2 dB 28.2 dB 48.0 ms 200.0 ms 144.0 ms 99 ms/dB 0.6 ms/dB 6.0 dB 8.5 ms/dB 6.0 dB 8.5 ms/dB 12.0 dB 21.3 ms/dB 12.0 dB 21.3 ms/dB
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Codec Table 19 Basic Coefficient Set (cont'd) CMD Sequence COP_C COP_C COP_C COP_C COP_C COP_C COP_C COP_C COP_D COP_D COP_D COP_D COP_D COP_D COP_D COP_D COP_E COP_E COP_E COP_E COP_E COP_E COP_E COP_E COP_F COP_F COP_F COP_F COP_F COP_F COP_F COP_F Coefficient LIMX, LIMR OFFX OFFR LP2LX LP2LR LP1X LP1R reserved 00H PDSX PDNX LP2SX LP2NX PDSR PDNR LP2SR LP2NR LGAX COMX AAX AGX TMHX TMLX NOISX AGIX LGAR COMR AAR AGR TMHR TMLR NOISR AGIR Code 44H 0CH 0CH 20H 20H E1H E1H 26H F4H 20H 44H 26H F4H 20H 44H 13H C3H 20H 01H 0AH 24H 4FH 20H 12H B2H 55H 00H 0AH 2FH 4FH Value - 54 dB, - 54 dB 4.5 dB 4.5 dB 12 dB 12 dB 4.0 ms 4.0 ms 102.3 ms 32.0 ms 6.6 s 30.0 ms 102.3 ms 32.0 ms 6.6 s 30.0 ms 4.50 dB - 20.4 dB 12.0 dB 12.0 dB 14.0 ms/dB 383.0 ms/dB - 66.2 dB 0 dB 5.5 dB - 15.1 dB - 33.2 dB 18.1 dB 14.0 ms/dB 500.9 ms/dB - 66.23 dB 0 dB
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Codec 4.5 Controlled Monitoring
A so called "controlled monitoring" can be done when the bit GCR.CME is set. This mode can only be used together with the speakerphone mode (GCR.SP). With CME = '1' the attenuation stage GHR is fixed to a value of 0 dB but the attenuation takes place in the analog loudspeaker amplifier ALS in a way that the amplification of the ALS is set to - 9.5 dB or -21.5 dB (depends on ATCR.CMAS setting) as soon as the attenuation control unit switches to transmit mode. Therefore in transmit direction the same behavior as in speakerphone mode occurs but in the receive direction the handset output offers a signal as in normal handset mode while the volume at the loudspeaker output will be reduced to a low level during transmit mode. If the programming for the loudspeaker output (ARCR.LSC) is already chosen for values of less or equal - 9.5 dB, no further attenuation takes place. In order to get a stable controlled monitoring due to the feedback of the microphone signal to the loudspeaker via the sidetone stage it is possible to change the tap of the sidetone signal from before to after the attenuation stage (PFCR.PGZ = '1'). 4.6 Voice Data Manipulation
The codec offers several possibilities of manipulating and controlling the codec data to support a variety of applications and operating modes. All the functions and modes can be selected by setting the register bits listed in table 20. The signal paths and functions are illustrated in the voice data manipulation block of figure 62. Possible applications and operating modes which can be realized by the voice data manipulation of the codec together with the time slot and data port selection of the integrated IOM-2 Handler are e.g.: * Three party conferencing with - 1 device internal and 2 external subscribers or - 2 device internal, tip-ring extension and 1 external subscriber The addition of the subscriber information can be done completely in the terminal by the integrated codec * Communication between codec and other voice data processing devices on IOM-2 (e.g. ACE, Jade, SAM and ISAR) * The data formats PCM A-Law PCM -Law 8-bit Linear and 16-bit Linear are provided. The 8-bit formats of CH1 and CH2 in both directions can be masked by an implemented mask register * Monitoring a running phone call
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Codec * Intercommunication: During a running phone call a voice announcement or a query can be switched or added to the desired outputs (handset, loudspeaker or transmit direction) Table 20 Voice Data Manipulation Register Bits Description As data source for the transmit data channels CH1X or CH2X respectively can be selected: - Codec voice data XDAT - Addition of XDAT and the receive channel CH2R or CH1R respectively. - Receive channel CH2R or CH1R respectively - Idle code The data of the receive channels can be attenuated individually by ATT1R, ATT2R to ensure an acceptable speech quality in the three party conferencing DSSR DSS1X, DSS2X: Data Source Data Source Selection Register Selection CH1X, Data Source Selection CH2X
DSSR: As data source for the codec receive data Data Source channel RDAT can be selected: Selection Receive - Receive channel CH1R - Receive channel CH2R - Addition of CH1R and CH2R - Idle code ENX1, ENX2: Enable Transmit CH1, CH2 DFR Data Format Register DF1R, DF2R: Data Format CH1R, CH2R The transmit data of CH1X, CH2X can be enabled or disabled The data format A-Law -Law 8-bit linear and 16-bit linear can be selected An 8-bit linear code can be selected for transmit and receive separately The 8-bit formats of CH1 and CH2 in both directions can be masked by an implemented mask register
8LIN1, 8LIN2: 8-bit Linear CH1, 8-bit Linear CH2 MASK1, MASK2: MASK1R, Mask Data CH1, MASK2R Mask Channel 1,2 CH2 Register
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Codec 4.7 Test Functions
The codec provides several test and diagnostic functions which can be grouped as follows: * * * * * * * * All programmable configuration registers and coefficient RAM-locations are readable Digital loop via PCM-register (DLP) Digital loop via signal processor (DLS) Digital loop via noise shaper (DLN) Analog loop via analog front end (ALF) Analog loop via converter (ALC) Analog loop via noise shaper (ALN) Analog loop via Z-sidetone (ALZ); sidetone gain stage GZ must be enabled (PFCR.GZ = 1) and sidetone gain must be programmed with 0 dB; depending on the DSSR bit setting in the Data Source Selection Register (DSSR) an addition to the incoming voice signal is executed.
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Codec 4.8 Programming of the Codec
During initialization of the codec a subset of configuration registers and coefficient RAM (CRAM) locations has to be programmed to set the configuration parameters according to the application and desired features. The codec can be programmed via microcontroller interface (see chapter 2.1) or the IOM-2 MONITOR channel (see chapter 2.2.4). The coefficient RAM (CRAM) can generally be programmed in power-up as well as in power-down mode. However, due to the general possibility of concurrent accesses of the ARCOFI(R)-DSP and the microcontroller, access collisions can not totally be eliminated. To ensure the error free programming of the CRAM, it's recommended to delay the access after switching from power-down to power-up ( or after switching from power-up to power-down respectively) by a setup time of 4 IOM-2 frames plus the setup time of the oscillator, i.e in total about 5 ms. An ARCOFI(R) compatible programming sequence is available (see chapter 2.1.1.1 and chapter 4.8.1) which allows using the SOP, COP and XOP command sequences of the ARCOFI. The codec can also be programmed by addressing the configuration registers and coefficient RAM (CRAM) locations directly (see chapter 4.8.2). The following two chapters 4.8.1 and 4.8.2 give an overview of the access to the codec parameters. For more detailed information about the individual parameters refer to the corresponding sections in the functional and register description of the codec. 4.8.1 Indirect Programming of the Codec (SOP, COP, XOP)
This programming sequence is compatible to the SOP, COP and XOP command sequences of the ARCOFI. It gives indirect access to the codec registers 60H-6EH and the CRAM (80H-FFH). The codec command word (cmdw) is followed by a defined number of data bytes (data n; n = 0, 1, 4 or 8). The number of data bytes depends on the codec command. The commands can be applied in any order and number. The coding of the different SOP, COP and XOP commands is listed in the description of the command word (CMDW) in chapter 4.8.1.1. Structure of the ARCOFI compatible sequence:
defined length defined length cmd data1 data n
00H
cmdw
data1
data n
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Codec 4.8.1.1 Description of the Command Word (CMDW) 0 0 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0
Value after reset: BFH 7 CMDW R/W CMDx 0: 1: R/W
writing to configuration registers or to coefficient RAM reading from configuration registers or from coefficient RAM
Address to internal programmable locations CMD 5 4 3 2 1 0 0 0 X X X X code reserved 0 1 X X X X status operation (SOP) 1 0 X X X X coefficient operation (COP) 1 1 X X X X extended operation (XOP)
Coding of Status Operations (SOP): Bit 3 2 1 0 CMD Name Status CMD Seq. Len. CMD Sequence Description (Registers being accessed) ..
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SOP_0 SOP_1 SOP_2 SOP_3 SOP_4 SOP_5 SOP_6 SOP_7 SOP_8 SOP_9 SOP_A SOP_B SOP_C SOP_D SOP_E SOP_F
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 9
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Codec Coding of Coefficient Operations (COP)
Bit 3 2 1 0 CMD Name COP_0 COP_1 Status CMD Seq. Len. 9 9 CMD Sequence Description <..> <..> <..> <..> <..> <..> .. .. .. .. .. .. .. .. .. .. Comments
0 0
0 0
0 0
0 1
R/W R/W
Tone generator 1 Tone generator 2 Additional TG gain Tone generator 3 Dual tone frequency Tone filter Control generator Transmit gain Receive gain Conferencing Atten. Sidetone gain Correction filter FX Correction filter FR Coefficients for Speakerphone
0
0
1
0
COP_2
R/W
9
0 0 0
0 1 1
1 0 0
1 0 1
COP_3 COP_4 COP_5
R/W R/W R/W
5 5 9
0 0 1 1 1 1 1 1 1 1
1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1
COP_6 COP_7 COP_8 COP_9 COP_A COP_B COP_C COP_D COP_E COP_F
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
5 9 9 9 9 9 9 9 9 9
AGC transmit AGC receive
Coding of Extended Operations (XOP)
Bit 3 2 1 0 CMD Name XOP_6 Status CMD Seq. Len. 6 Comments
0
1
1
0
R/W
1
1
1
1
XOP_F
R/W
1
Sequence for volume control of the loudspeaker (SEQ = ) No operation (NOP)
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Codec 4.8.2 Direct Programming of the Codec
The codec registers (60H-6FH) and the CRAM (80H-FFH) are directly accessible (see chapter 2.1 and 4.8.2.1). 4.8.2.1 CRAM Back-Up Procedure
For the direct access to individual CRAM coefficients via microcontroller a back-up procedure is provided. This ensures that the codec DSP always works with a consistent and valid coefficient block during the changing of CRAM parameters. The following section describes this back-up procedure. Note: For the ARCOFI compatible programming sequence (see chapter 2.1.1.1) such a back-up procedure for the CRAM blocks is not necessary because it is done automatically. The control of the back-up procedure is done with the CRAM Control Register (CCR) and the CRAM Status Register (CSR).The Control and Status bits in these registers are explained in the following section: CRAM Block Address (CBADR) The CRAM range (80H to FFH) is subdivided in 16 CRAM blocks with the block address CBADR = '0H' to 'FH'. Each coefficient block has 8 bytes. The mapping of the CRAM coefficients corresponds to the COP_x sequences of the ARCOFI (see table 22 and chapter 4.8.1.1). DSP CRAM Access (DCA) By setting this bit it is possible to select whether the codec DSP has access to the CRAM blocks in the normal CRAM range ('0') or to a temporary 8-byte CRAM block ('1'). Start Back-up Procedure (SBP) Setting this bit starts the transfer of a CRAM block (CBADR) to the temporary 8-byte CRAM block. Busy Back-up Procedure (BSYB) This status bit indicates if a transfer of a CRAM block (CBADR) to the temporary 8-byte CRAM block is running ('1') or not ('0'). If the transfer is running no CRAM access via microcontroller interface is allowed. Figure 76 shows the access structure of CRAM and temporary CRAM. Figure 77 gives a signal flow of the back-up procedure of a CRAM block x (x = 0...F).
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Codec

Temporary CRAM
C Access
DCA = '0' DSP Access
Data Flow
DCA = '1'
Figure 76 CRAM Access Structure
Write: CCR.DCA = '1' CCR.SBP = '1' CCR.CBADR = 'x'' Start back-up procedure block x DSP access to temp. CRAM block as soon as transfer has completed Transfer busy
Read CSR.BSYB Back-up procedure busy? Transfer not busy
- C access to CRAM possible - Switching the DSP access between CRAM and temporary CRAM block is possible by DCA
Write Update CRAM block x
Write CCR.DCA = '0' DSP access to CRAM block x
Figure 77 Signal Flow of the Back-up Procedure
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Codec 4.8.3 Reference Tables for the Register and CRAM Locations Register Bit Effect
Table 21 Configuration Registers Address CMDW WR/RD SOP_0 60H 10H/90H GCR SP AGCX AGCR MGCR CME PU ATT2R Speakerphone ON/OFF TX-automatic gain control (if GCR.SP = 1) RX-automatic gain control (if GCR.SP = 1) Modified gain control receive Controlled monitoring enable Power-up/down mode Attenuation of the receive channel related to transmit channel 2 Attenuation of the receive channel related to transmit channel 1 TX digital gain RX digital gain Sidetone gain TX-frequency correction filter Position sidetone gain RX-frequency correction filter Disable high-pass (50 Hz) receive Disable high-pass (50 Hz) transmit Enable tone generator Dual tone mode Enable tone filter Pulsed tone Sequence generator Tone mode Stop mode Square/trapezoid shaped signal
ATT1R
SOP_1 61H 11H/91H PFCR GX GR GZ FX PGZ FR DHPR DHPX ET DT ETF PT SEQ TM SM SQTR
SOP_2 62H 12H/92H TGCR
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Codec Table 21 Configuration Registers (cont'd) Address CMDW WR/RD SOP_3 63H 13H/93H TGSR TRL TRR DTMF TRX SEM DHOP DHON DLSP DLSN SOP_5 65H 15H/95H ATCR MIC(7:4) CMAS AIMX(1:0) SOP_6 66H SOP_7 67H 17H/97H DFR DF2R(7:6) DF2X(5:4) DF1R(3:2) DF1X(1:0) Data format CH2 receive Data format CH2 transmit Data format CH1 receive Data format CH1 transmit 16H/96H ARCR HOC(7:4) LSC(3:0) Handset output amplifier control Loudspeaker output amplifier control Microphone amplifier control Reserved Controlled monitoring attenuation select Analog input multiplexer Reserved Tone ringing via loudspeaker Reserved Tone ringing in receive direction DTMF mode Tone ringing in transmit direction Reserved Reserved Reserved Single ended mode of loudspeaker amplifier Disable HOP (tristate) Disable HON (tristate) Disable LSP (tristate) Disable LSN (tristate) Register Bit Effect
SOP_4 64H 14H/94H ACR
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Codec Table 21 Configuration Registers (cont'd) Address CMDW WR/RD SOP_8 68H 18H/98H DSSR DSSR(7:6) ENX2 ENX1 DSS2X(3:2) DSS1X(1:0) PGCR PGCX ERA MAAR PGCR PGCX ERA SPST(1:0) -/99H XSR if MAAR = '1' Data source selection receive Enable transmit CH2 Enable transmit CH2 Data source selection CH2 Transmit Data source selection CH1 Transmit Position of gain control receive Position of gain control transmit Enhanced reverse attenuation Reserved Reserved Reserved Reserved Monitoring AGC Attenuation Receive Read-back position of gain control receive Read-back position of gain control transmit Read-back enhanced reverse attenuation Reserved Reserved Reserved Speakerphone state Value of the momentary AGC attenuation Register Bit Effect
SOP_9 69H 19H/XCR
-/99H
XSR if MAAR = '0'
SOP_A 6AH SOP_B 6BH 1BH/9BH MASK2R MASK2(7:2) Mask register CH2 MP2(1:0) Mask Position CH2 1AH/9AH MASK1R MASK1(7:2) Mask register CH1 MP1(1:0) Mask Position CH1
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Codec Table 21 Configuration Registers (cont'd) Address CMDW WR/RD SOP_C 6CH 1CH/9CH TFCR ALTF(5:3) DLTF(2:0) Reserved Reserved Analog Loops and test functions Digital Loops and test functions Reserved Reserved ARCOFI compatible sequence for WR/ RD of 8 bytes (Registers) Register Bit Effect
SOP_D 6DH SOP_E 6EH SOP_F 1FH/9FH WR/ CCR DCA SBP CBADR(3:0) DCA BSYB CBADR(3:0) 1EH/9EH TMR2 1DH/9DH TMR1
For the register below there is no command word available 6FH Reserved Reserved DSP CRAM access Start back-up procedure CRAM block address Reserved Reserved DSP CRAM access Busy back-up procedure CRAM block address
RD
CSR
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Codec Table 22 Coefficient RAM (CRAM) Address CMDW WR/RD 87H 86H 85H 84H 83H 82H 81H 80H 8FH 8EH 8DH 8CH 8BH 8AH 89H 88H 20H/A0H Mnemonic Description
COP_0: Tone generator parameter set 1 F1 G1 GD1 T1 21H/A1H F2 G2 GD2 T2 GTR GTX Tone generator frequency higher byte Tone generator frequency lower byte Tone generator amplitude Trapezoid generator amplitude Beat tone time higher byte Beat tone time lower byte Reserved Reserved Tone generator frequency higher byte Tone generator frequency lower byte Tone generator amplitude Trapezoid generator amplitude Beat tone time span higher byte Beat tone time span lower byte Level adjustment for receive path Level adjustment for transmit path
COP_1: Tone generator parameter set 2; tone generator level adjustment
COP_2: Tone generator parameter set 3; Parameter set for the DTMF-generator (TGSR.DTMF = 1) 97H 96H 95H 94H 93H 92H 91H 90H 9BH 9AH 99H 98H 22H/A2H F3 G3 GD3 T3 FD Tone generator frequency higher byte Tone generator frequency lower byte Tone generator amplitude Trapezoid generator amplitude Beat tone time span higher byte Beat tone time span lower byte Dual tone frequency higher byte Dual tone frequency lower byte Attenuation of the stop-band Center frequency Bandwidth Saturation amplification
COP_3: Tone filter 23H/A3H K A1 A2 GE
Data Sheet
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Codec Table 22 Coefficient RAM (CRAM) (cont'd) Address CMDW WR/RD A3H A2H A1H A0H AFH AEH ADH ACH ABH AAH A9H A8H B3H B2H B1H B0H BFH BEH BDH BCH BBH BAH B9H B8H 24H/A4H Mnemonic Description
COP_4: Control generator TON TOFF Turn-on period of the tone generator higher byte Turn-on period of the tone generator lower byte Turn-off period of the tone generator higher byte Turn-off period of the tone generator lower byte Transmit gain higher byte Transmit gain lower byte Receive gain higher byte Receive gain lower byte Conferencing attenuation CH1R Conferencing attenuation CH2R Reserved Reserved Sidetone gain higher byte Sidetone gain lower byte Reserved Reserved Transmit correction filter coefficients part 1 Transmit correction filter coefficients part 2 Transmit correction filter coefficients part 3 Transmit correction filter coefficients part 4 Transmit correction filter coefficients part 5 Transmit correction filter coefficients part 6 Transmit correction filter coefficients part 7 Transmit correction filter coefficients part 8
COP_5: Receive and transmit gain 25H/A5H GX GR ATT1R ATT2R 26H/A6H GZ 27H/A7H FX
COP_6:Sidetone gain
COP_7:Transmit correction filter part 5 to part 12
Data Sheet
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Codec Table 22 Coefficient RAM (CRAM) (cont'd) Address CMDW WR/RD Mnemonic Description
COP_8:Transmit correction filter part 1 to part 4 and receive correction filter part 9 to part 12 C7H C6H C5H C4H C3H C2H C1H C0H CFH CEH CDH CCH CBH CAH C9H C8H 28H/A8H FX Transmit correction filter coefficients part 9 Transmit correction filter coefficients part 10 Transmit correction filter coefficients part 11 Transmit correction filter coefficients part 12 Receive correction filter coefficients part 9 Receive correction filter coefficients part 10 Receive correction filter coefficients part 11 Receive correction filter coefficients part 12 Receive correction filter coefficients 1 Receive correction filter coefficients 2 Receive correction filter coefficients 3 Receive correction filter coefficients 4 Receive correction filter coefficients 5 Receive correction filter coefficients 6 Receive correction filter coefficients 7 Receive correction filter coefficients 8
FR
COP_9:Receive correction filter part 1 to part 8 29H/A9H FR
COP_A:Parameter set for transmit and receive speech comparator Parameter set for speakerphone control unit D7H D6H D5H D4H D3H D2H D1H D0H 2AH/AAH GAE GLE ATT ETAE ETLE TW DS SW Gain of acoustic echo Gain of line echo Attenuation programmed in GHR or GHX Echo time (acoustic side) Echo time (line side) Wait time Decay speed Switching time
Data Sheet
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Codec Table 22 Coefficient RAM (CRAM) (cont'd) Address CMDW WR/RD DFH DEH DDH DCH DBH DAH D9H D8H E7H E6H E5H E4H E3H E2H E1H E0H EFH EEH EDH ECH EBH EAH E9H E8H Mnemonic Description
COP_B:Parameter set for transmit and receive speech comparator 2BH/ABH GDSAE PDSAE GDNAE PDNAE GDSLE PDSLE GDNLE PDNLE 2CH/ACH LIM OFFX OFFR LP2LX LP2LR LP1X LP1R 2DH/ADH PDSX PDNX LP2SX LP2NX PDSR PDNR LP2SR LP2NR Reserve when speech is detected (acoustic side) Peak decrement when speech is detected (acoustic side) Reserve when noise is detected (acoustic side) Peak decrement when noise is detected (acoustic side) Reserve when speech is detected (line side) Peak decrement when speech is detected (line side) Reserve when noise is detected (line side) Peak decrement when noise is detected (line side) Starting level of the logarithmic amplifiers Level offset up to detected noise (transmit) Level offset up to detected noise (receive) Limitation for LP2 (transmit) Limitation for LP2 (receive) Time constant LP1 (transmit) Time constant LP1 (receive) Reserved Time constant PD for signal (transmit) Time constant PD for noise (transmit) Time constant LP2 for signal (transmit) Time constant LP2 for noise (transmit) Time constant PD for signal (receive) Time constant PD for noise (receive) Time constant LP2 for signal (receive) Time constant LP2 for noise (receive)
COP_C:Parameter set for transmit and receive speech detector
COP_D:Parameter set for receive and transmit speech detector
Data Sheet
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Codec Table 22 Coefficient RAM (CRAM) (cont'd) Address CMDW WR/RD F7H F6H F5H F4H F3H F2H F1H F0H FFH FEH FDH FCH FBH FAH F9H F8H Mnemonic Description
COP_E:Parameter set for transmit AGC 2EH/AEH LGAX COMX AAX AGX TMHX TMLX NOISX AGIX 2FH/AFH LGAR COMR AAR AGR TMHR TMLR NOISR AGIR Loudness gain adjustment Compare level rel. to max. PCM-value Attenuation range of automatic control Gain range of automatic control Settling time constant for higher levels Settling time constant for lower levels Threshold for AGC-reduction by background noise Initial AGC gain transmit Loudness gain adjustment Compare level rel. to max. PCM-value Attenuation range of automatic control Gain range of automatic control Settling time constant for higher lower levels Settling time constant for lower levels Threshold for AGC-reduction by background noise Initial AGC attenuation/gain receive
COP_F:Parameter set for receive AGC
Data Sheet
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Clock Generation 5 Clock Generation
Figure 78 shows the clock system of the SCOUT. The oscillator is used to generate a 15.36 MHz clock signal. The DPLL generates the IOM-2 clocks FSC (8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received UPN frames (see figure 79). The prescaler for the microcontroller clock output (MCLK) divides the 15.36 MHz clock by 1, 2 and 8 corresponding to the MCLK control bits in the MODE1 register. Additionally it is possible to disable the MCLK output by setting the MCLK bits to '11'. With the CDS bit (Clock Divider Selection) in the MODE1 register a double clock rate for the MCLK output can be selected. .
XTAL 15.36 MHz
OSC
15.36 MHz
DPLL
FSC DCL BCL 3
'0': x = 2 MODE1.CDS = '1': x = 1
x CPLL Codec Clock
Reset Generation C/I change EAW Watchdog Undervoltage Detection
125 s < t < 250 s 125 s < t < 250 s t = 125 s t = 64 ms
MCLK Prescaler '00': '01': '10': '11': 2 8 1 MCLK disabled MCLK
MODE1.MCLK
clock_gen_p.vsd
Figure 78 Clock System of the SCOUT
Data Sheet
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Clock Generation 5.1 5.1.1 Jitter Jitter on IOM-2
The receive PLL readjusts, if the integrator function is enabled (TR_CONF1.RPLL_INTD = '0') if six consecutive pulses on the UPN interface deviate in the same direction. If the integrator function is disabled by setting TR_CONF1.RPLL_INTD to '1' this is done after the deviation of every pulse. Adjusting on the positive and negative pulses is done by adding/subtracting 1 XTAL from/to the DCL clock. 5.1.2 Jitter on UPN
The UPN transmit clock is derived from the UPN receive clock. 5.1.3 Jitter on MCLK
Jitter on the MCLK output is directly related to the crystal tolerance. Only clock dividers are involved.
FSC DCL BCL
Figure 79 Clock waveforms
Data Sheet
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Reset 6 Reset
The SCOUT can be reset completely by a hardware reset (pin RST) or by the integrated undervoltage detection circuit. Additionally each functional block can be reset separately via register SRES. If enabled an exchange awake, subscriber awake, watchdog timeout or undervoltage detection can generate a reset on pin RSTO/SDS2. A hardware reset always generates a reset on pin RSTO/SDS2 (see figure 80).
SDSx_CR Register
SDSx SDS2 RSS(2:1) = '01'
SDS1 Pin
C/I Code Change (Exchange Awake) EAW (Subscriber Awake) Watchdog
125 s < t < 250 s 125 s < t < 250 s
t = 125 s VDDDET Pin RSS1='1'
'1' RSS2='0'
RSTO/ SDS2 Pin
Undervoltage Detection/ t = 64 ms Power On Reset
'0'
Software Reset (Register SRES) Reset Functional Block Block HDLC: TR: IOM: MON: CO: CPLL: Register (00H-2FH) (30H-3BH) (40H-5BH) (5CH-5FH) (60H-6FH) -
Reset MODE1 Register
Internal Reset of all Registers RST Pin
Res_Gen_p.vsd
Figure 80 Reset Generation. The above mentioned reset pulse widths are controlled by the clock pin FSC
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Reset 6.1 Reset Source Selection
The internal reset sources C/I code change, EAW and Watchdog can be output at the low active reset pin RSTO/SDS2. The selection of these reset sources can be done with the RSS2,1 bits in the MODE1 register according table 23. If RSS2,1 = '01' the RSTO/SDS2 pin has SDS2 functionality and a serial data strobe signal (see chapter 2.2.3) is output at the RSTO/SDS2 pin. In this case only a hardware reset or a reset generated by the undervoltage detection is output at RSTO/SDS2. The internal reset sources set the MODE1 register to its default value. Table 23 Reset Source Selection RSS2 Bit 1 0 0 1 1 RSS1 Bit 0 0 1 0 1 C/I Code Change --EAW --Watchdog Timer ---SDS2 Functionality --
x
---
x
--
x
--
x
* C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/ I0) generates a reset pulse of 125s t 250s. * EAW (Subscriber Awake) A low pulse of at least 65 ns pulse width on the EAW input starts the oscillator from the power down state and generates a reset pulse of 125 s t 250 s. * Watchdog Timer After the selection of the watchdog timer (RSS = '11') an internal timer is reset and started. During every time period of 128 ms the microcontroller has to program the WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer: WTC1 1. 2. 1 0 WTC2 0 1
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse of 125 s is generated. If the watchdog timer is enabled (RSS = '11') the RSS bits can only be changed by a hardware reset.
Data Sheet
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Reset 6.2 Undervoltage Detection (VDDDET)
The integrated undervoltage detection circuit can be enabled or disabled by pinstrapping the VDDDET pin to'VSS' or 'VDD' respectively. It monitors the voltage level of the supply voltage (5V or 3.3 V) and sets RSTO to 'low' if the supply voltage falls below the detection level VDET. When the supply voltage returns to a higher voltage than the detection level plus hysteresis (VDET+VHYS) the reset is released if the deactivation time tDEACT expires (64 ms). The specified detection level VDET and the hysteresis VHYS for VDD = 3.3V (Pin VDDSEL = 'VSS') or VDD = 5V (Pin VDDSEL = 'VDD') respectively are listed in table 24.
.
Table 24 Levels of the Undervoltage Detection Parameter Limit Values VDD=3.3V5% min. max. 2.9V VDD/30 Limit Values VDD=5V5% min. 4.2V VDD/40 max. 4.5V VDD/30
VDET
Hysteresis VHYS
2.7V VDD/40
Above the minimum operating voltage of the undervoltage detection (1.5V) the reset output RSTO is in a defined state and acts as a power-on reset for the system. If the supply voltage falls below VDET the microcontroller clock MCLK is stopped (MCLK = 'low') and all registers are reset by the internal reset. The MCLK is stopped immediately which may result in a shorter high period of the clock signal. If the supply voltage exceeds VDET+VHYS the internal reset is released and the MCLK is output with its default frequency. The external reset pulse is extended by 64 ms due to the oscillator start until a stable clock is achieved. The maximum delay for the activation of the undervoltage detection tACT is 10 s. The maximum rising/falling edge of the supply voltage for activation/deactivation of the undervoltage detection is 0.1V/s. Figure 81 shows the undervoltage control timing.
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Reset
Figure 81 Undervoltage Control Timing 6.3 External Reset Input
At the active low RST input pin an external reset can be applied forcing the device into the reset state. This external reset signal is additionally fed to the RSTO/SDS2 output. The length of the reset signal is specified in chapter 8.1.8. After a reset of the undervoltage detection or an external reset (RST) all internal registers are set to their reset values (see register description in chapter 7). 6.4 Software Reset Register (SRES)
Every internal functional block can be reset separately by setting the corresponding bit in the SRES register (see chapter 7.1.13). The reset state is activated as long as the bit is set to '1'. The address range of the registers which will be reset at each SRES bit is listed in figure 80.
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Reset 6.5 Pin Behavior during Reset
During each reset the reference voltage (VREF) stays applied, the oscillator and data clocks (DCL) keep running. During a reset caused by the undervoltage detection the microcontroller clock (pin MCLK) is stopped. In all other cases the microcontroller clock is running. During any reset that has an influence on the IOM handler (see figure 80) the pin FSC is set to '1', the pin SDS1 is set to '0' and pin BCL, DD and DU are in the high-impedance state. During any reset that has an influence on the codec (see figure 80) the pins LSP, LSN, HOP and HON are in the high-impedance state. During any reset that has an influence on the transceiver (see figure 80) the pins LIa and LIb are in the high-impedance state. During hardware reset or a reset caused by the undervoltage detection the pins SDX and INT are in the high-impedance state. A hardware reset and a reset caused by the undervoltage detection is always output at pin RSTO/SDS2. This reset will be released by the falling edge of BCL following the release of the pin RST (if the undervoltage detection is disabled) or after 64 ms (if the undervoltage detection is enabled).
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Detalled Register Description 7 Detailed Register Description
FFH
The register mapping is shown in Figure 82.
Codec Coefficient RAM
80H 70H 60H
Reserved Codec Configuration IOM Handler (CDA, TSDP, CR, STI), MONITOR Register Transc., Interrupt, Mode Reg. HDLC Control, CI Reg. HDLC RFIFO/XFIFO
40H 30H 20H
00H
Figure 82 Register Mapping The register address range from 00-1FH is assigned to the two FIFOs having an identical address range. The address range 20-2FH pertains to the HDLC controller and the CI handler. The register set ranging from 30-3FH pertains to the transceiver, interrupt and general configuration registers. The address range from 40-59H is assigned to the IOM handler with the registers for timeslot and data port selection (TSDP) and the control registers (CR) for the codec data (CO), transceiver data (TR), Monitor data (MON), HDLC/CI data (HCI) and controller access data (CDA), serial data strobe signal (SDS), IOM interface (IOM) and synchronous transfer interrupt (STI). The address range from 5C-5FH pertains to the MONITOR handler. The codec configuration registers and the codec coefficient RAM (CRAM) are assigned to the address range 60-6FH or 80-FFH respectively. The register summaries are shown in the following tables containing the abbreviation of the register name and the register bits, the register address, the reset values and the register type (Read/Write). A detailed register description follows these register summaries. The register summaries and the description are sorted in ascending order of the register address.
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Detalled Register Description
HDLC Control Registers, CI Handler Name RFIFO XFIFO ISTAH MASKH STAR CMDR RME RME RPF RPF 7 6 5 4 3 2 1 0 ADDR R/WRES 00H-1FH R 00H-1FH W 0 0 XACI 0 0 0 20H 20H 21H 21H 22H 23H 24H 0 0 MHA MLA RBC0 0 0 OV RBC11 TEI1 TEI2 VFR 0 RDO 0 CRC 0 RAB 0 SA1 0 SA0 0 C/R 0 RBC8 EA EA TA TLP 25H 26H 26H 27H 27H 28H 28H 29H 2AH2DH CIC1 S/G BAS BAC 0 2EH 2EH 2FH 2FH R F3H W FEH R FCH W FEH
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D-Channel Receive FIFO D-Channel Transmit FIFO RFO RFO 0 0 XPR XPR 0 STI 0 XMR XMR RACI XTF RAC XDU XDU 0 0
R 10H W FCH R 40H W 00H R/W C0H R/W 00H R/W 00H W FCH W FCH R 00H R 00H W FFH W FFH R 0EH R/W 00H
XDOV XFW RMC RRES
XME XRES
MODEH MDS2 MDS1 MDS0 EXMR TIMR SAP1 SAP2 RBCL RBCH TEI1 TEI2 RSTA TMH RBC7 0 XFBS RFBS CNT
DIM2 DIM1 DIM0 0 ITF
SRA XCRC RCRC VALUE SAPI1 SAPI2
Reserved CIR0 CIX0 CIR1 CIX1
Data Sheet
CODR0 CODX0 CODR1 CODX1
CIC0
TBA2 TBA1 TBA0 0
CICW CI1E
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Detalled Register Description
Transceiver, Interrupt, General Configuration Registers NAME TR_ CONF0 7 DIS_ TR 6 0 1 0 5 0 EN_ SFSC 0 0 4 3 2 0 0 0 1 0 1 0 0 LDD 0 0 ADDR R/WRES 30H 31H 32H 33H 34H 35H 36H37H RIC RIC 0 1 0 1 38H 39H 3AH3BH 3CH 3CH R 01H W 7FH R 00H R/W 7FH R/W 00H R/W 62H R/W 00H R 00H R/W 00H R/W
TCM L1SW 0 TRS RDS 0 0 0 RLP 0
TR_ RPLL_ CONF1 INTD TR_ CONF2 TR_STA TR_CMD DIS_ TX RINF
FSYN FCV MSYN PD LP_A 0
XINF
Reserved Reserved ISTATR MASKTR 0 0 x 1 x 1 x 1 LD LD
Reserved ISTA MASK MODE1 MODE2 ID SRES 0 0 0 0 0 ST ST CIC CIC TIN TIN WOV TRAN MOS HDLC WOV TRAN MOS HDLC RSS2 RSS1 0
MCLK 0 0 0
CDS WTC1 WTC2 CFS 0 0 0 DREF
3DH R/W 00H
PPSDX 3EH R/W 00H 3FH 3FH R 0xH W 00H
DESIGN RES_ RES_ RES_ RES_ RES_ RES_ CPLL MON HDLC IOM TR CO
Data Sheet
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Detalled Register Description
IOM Handler (Timeslot , Data Port Selection, CDA Data and CDA Control Register) Name CDA10 CDA11 CDA20 CDA21 CDA_ TSDP10 CDA_ TSDP11 CDA_ TSDP20 CDA_ TSDP21 CO_ TSDP10 CO_ TSDP11 CO_ TSDP20 CO_ TSDP21 DPS DPS DPS DPS DPS DPS DPS DPS 7 6 5 4 3 2 1 0 ADDR R/WRES 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H R/W FFH R/W FFH R/W FFH R/W FFH R/W 00H R/W 01H R/W 80H R/W 81H R/W 80H R/W 81H
Controller Data Access Register (CH10) Controller Data Access Register (CH11) Controller Data Access Register (CH20) Controller Data Access Register (CH21) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS TSS TSS TSS TSS TSS TSS TSS TSS TSS
4AH R/W 81H 4BH R/W 85H 4CH R/W 00H 4DH R/W 01H
TR_ DPS TSDP_B1 TR_ DPS TSDP_B2
Data Sheet
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Detalled Register Description Name CDA1_ CR CDA2_ CR 7 0 0 6 0 0 5 4 3 2 1 0 ADDR R/WRES 4EH R/W 00H 4FH R/W 00H
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP TBM EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP TBM
IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler Name CO_CR TR_CR HCI_CR 7 0 0 DPS_ CI1 6 0 0 EN_ CI1 EN_ MON 5 0 EN_ D EN_ D 0 4 0 EN_ B2R EN_ B2H 0 0 0 TIC_ DIS 3 2 1 0 ADDR R/WRES 50H 51H 52H 53H 54H 55H DIS_ IOM 56H 57H 58H 58H 59H R/W 00H R/W 3EH R/W A0H R/W 40H R/W 00H R/W 00H R/W 00H R FFH R 00H W 00H R/W FFH
EN21 EN20 EN11 EN10 EN_ B1R EN_ B1H 0 EN_ B2X 0 0 TSS TSS EN_ CLKM DIS_ BCL OD MCDA11 STI 21 ACK 21 STI 21 STI 20 ACK 20 STI 20 EN_ B1X 0 MCS 0 0
MON_CR DPS
SDS1_CR ENS_ ENS_ ENS_ TSS TSS+1 TSS+3 SDS2_CR ENS_ ENS_ ENS_ TSS TSS+1 TSS+3 IOM_CR MCDA STI ASTI MSTI SPU 0 0
MCDA21
MCDA20
MCDA10 STI 11 ACK 11 STI 11 STI 10 ACK 10 STI 10
STOV STOV STOV STOV 21 20 11 10 0 0 0 0
STOV STOV STOV STOV 21 20 11 10
Data Sheet
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Detalled Register Description Name SDS_ CONF 7 0 6 0 5 0 4 0 3 0 2 0 1 0 ADDR R/WRES
SDS2_ SDS1_ 5AH R/W 00H BCL BCL 5BH 5CH 5CH 0 0 0 0 0 0 TOUT TOUT 5DH R FFH W FFH R 00H
Reserved MOR MOX MOSR MOCR MSTA MCONF MDR MRE 0 0 MER MRC 0 0 MONITOR Receive Data MONITOR Transmit Data MDA MIE 0 0 MAB MXC 0 0 0 0 0 0 0 0 MAC 0
5EH R/W 00H 5FH 5FH R 00H W 00H
Codec Configuration Register Name GCR PFCR TGCR TGSR ACR ATCR ARCR DFR DSSR XCR XSR DF2R DSSR 7 SP GX ET 0 0 6 5 4 3 2 PU FR TM 1 0 ADDR R/WRES 60H 61H 62H 63H 64H 65H 66H DF1X DSS1X 0 MAAR SPST 67H 68H 69H 69H 69H R/W 00H R/W 00H R/W 00H R/W 00H R/W 00H R/W 00H R/W 00H R/W 00H R/W 00H W 00H R 00H R 00H
AGCX AGCR MGCR CME GR DT TRL 0 MIC HOC DF2X ENX2 ENX1 0 0 GZ ETF 0 0 FX PT PGZ SEQ
ATT2R ATT1R DHPR DHPX SM 0 SQTR 0
TRR DTMF TRX
SEM DHOP DHON DLSP DLSN 0 CMAS LSC DF1R DSS2X 0 0 0 0 AIMX
PGCR PGCX ERA PGCR PGCX ERA
Momentary AGC Attenuation (if XCR.MAAR = '1')
Data Sheet
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Detalled Register Description MASK1R MASK2R TFCR 0 0 MASK1 MASK2 ALTF Reserved Reserved CCR CSR Name 0 0 7 0 0 6 DCA SBP CBADR CBADR 3 2 1 0 MP1 MP2 DLTF 6AH R/W 00H 6BH R/W 00H 6CH R/W 00H 6DH 6EH 6FH 6FH W 00H R 00H
DCA BSYB 5 4
ADDR R/WRES 70H7EH
Reserved NOP 1 1 1 1 1 1 1 1
7FH
R FFH
After an ISTAH.RME interrupt, the number of received bytes can be obtained by reading the RBCL register. 7.0.1 XFIFO - Transmit FIFO 7 XFIFO Transmit data 0 WR (00H-1FH)
A write access to any address within the range 00-1FH gives access to the "current" FIFO location selected by an internal pointer which is automatically incremented after each write access. This allows the use of efficient "move string" type commands by the microcontroller. Depending on EXMR.XFBS up to 16 or 32 bytes of transmit data can be written to the XFIFO following an ISTAH.XPR interrupt.
Data Sheet
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Detalled Register Description 7.0.2 ISTAH - Interrupt Status Register HDLC
Value after reset: 10H 7 ISTAH RME RME RPF RFO XPR XMR XDU 0 0 0 RD (20H)
... Receive Message End
One complete frame of length less than or equal to the defined block size (EXMR.RFBS) or the last part of a frame of length greater than the defined block size has been received. The contents are available in the RFIFO. The message length and additional information may be obtained from RBCH and RBCL and the RSTA register. RPF ... Receive Pool Full
A data block of a frame longer than the defined block size (EXMR.RFBS) has been received and is available in the RFIFO. The frame is not yet complete. RFO ... Receive Frame Overflow
The received data of a frame could not be stored, because the RFIFO is occupied. The whole message is lost. This interrupt can be used for statistical purposes and indicates that the microcontroller does not respond quickly enough to an RPF or RME interrupt (ISTAH). XPR ... Transmit Pool Ready
A data block of up to the defined block size (EXMR.XFBS) can be written to the XFIFO. An XPR interrupt will be generated in the following cases: * after an XTF or XME command as soon as the 16 or 32 respectively bytes in the XFIFO are available and the frame is not yet complete * after an XTF together with an XME command is issued, when the whole frame has been transmitted XMR ... Transmit Message Repeat
The transmission of the last frame has to be repeated because a collision has been detected after the 16th/32th data byte of a transmit frame. XDU ... Transmit Data Underrun
The current transmission of a frame is aborted by transmitting seven '1's because the XFIFO holds no further data. This interrupt occurs whenever the microcontroller has failed to respond to an XPR interrupt (ISTAH register) quickly enough, after having initiated a transmission and the message to be transmitted is not yet complete.
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Detalled Register Description 7.0.3 MASKH - Mask Register HDLC
Value after reset: FCH
7 MASKH RME RPF RFO XPR XMR XDU 0
0 0 WR (20H)
Each interrupt source in the ISTAH register can be selectively masked by setting to '1' the corresponding bit in MASK. Masked interrupt status bits are not indicated when ISTAH is read. Instead, they remain internally stored and pending, until the mask bit is reset to '0'. 7.0.4 STAR - Status Register
Value after reset: 40H 7 STAR XDOV XDOV XFW 0 0 RACI 0 XACI 0 0 RD (21H)
... Transmit Data Overflow
More than 16/32 bytes have been written in one pool of the XFIFO, i.e. data has been overwritten. XFW ... Transmit FIFO Write Enable
Data can be written in the XFIFO. This bit may be polled instead of (or in addition to) using the XPR interrupt. RACI ... Receiver Active Indication
The HDLC receiver is active when RACI = '1'. This bit may be polled. The RACI bit is set active after a begin flag has been received and is reset after receiving an abort sequence. XACI ... Transmitter Active Indication
The HDLC-transmitter is active when XACI = '1'. This bit may be polled. The XACI-bit is active when an XTF-command is issued and the frame has not been completely transmitted.
Data Sheet
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Detalled Register Description 7.0.5 CMDR - Command Register
Value after reset: 00H 7 CMDR RMC RMC RRES 0 STI XTF 0 XME 0 XRES WR (21H)
... Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By setting this bit, the microcontroller confirms that it has fetched the data, and indicates that the corresponding space in the RFIFO may be released. RRES ... Receiver Reset
HDLC receiver is reset, the RFIFO is cleared of any data. STI ... Start Timer
The hardware timer is started when STI is set to one. The timer may be stopped by a write to the TIMR register. XTF ... Transmit Transparent Frame
After having written up to 16 or 32 bytes (EXMR.XFBS) in the XFIFO, the microcontroller initiates the transmission of a transparent frame by setting this bit to '1'. Except in the extended transparent mode the opening flag is automatically added to the message. XME ... Transmit Message End
By setting this bit to '1' the microcontroller indicates that the data block written last in the XFIFO completes the corresponding frame. Except in the extended transparent mode the transmission is terminated by appending the CRC and the closing flag sequence to the data. XRES ... Transmitter Reset
HDLC transmitter is reset and the XFIFO is cleared of any data. This command can be used by the microcontroller to abort a frame currently in transmission. Note: After an XPR interrupt further data has to be written to the XFIFO and the appropriate Transmit Command (XTF) has to be written to the CMDR register again to continue transmission, when the current frame is not yet complete (see also XPR in ISTAH). During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing mechanism is done automatically except in the extended mode.
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Detalled Register Description 7.0.6 MODEH - Mode Register
Value after reset: C0H 7 MODEH MDS2-0 MDS2 MDS1 MDS0 ... Mode Select 0 RAC DIM2 DIM1 0 DIM0 RD/WR (22H)
Determines the message transfer mode of the HDLC controller, as follows:
MDS2-0 Mode Number of Address Comparison Address 1.Byte 2.Byte Bytes Remark
0 0 0 0 1
0 0 1 1 0
0 Reserved 1 Reserved 0 Non-Auto
mode 1 2 TEI1,TEI2 SAP1,SAP2,SAPG - One-byte address compare.
1 Non-Auto
mode
TEI1,TEI2,TEIG Two-byte address compare.
0 Extended
transparent mode
1
1
0 Transparent -
mode 0
-
-
No address compare. All frames accepted. High-byte address compare.
1 1
1 0
1 Transparent > 1
mode 1
SAP1,SAP2,SAPG -
-
1 Transparent > 1
mode 2
TEI1,TEI2,TEIG Low-byte address compare.
Note: SAP1, SAP2: two programmable address values for the first received address byte (in the case of an address field longer than 1 byte); SAPG = fixed value FC / FEH. TEI1, TEI2: two programmable address values for the second (or the only, in the case of a one-byte address) received address byte; TEIG = fixed value FFH Two different methods of the high byte and/or low byte address comparision can be selected by setting SAP1.MHA and/or SAP2.MLA (see also description of these bits in chapter 7.0.9 or 7.0.11 respectively)
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Detalled Register Description RAC ... Receiver Active
The HDLC receiver is activated when this bit is set to '1'. If it is '0' the HDLC data is not evaluated in the receiver. DIM2-0 ... Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit enables/disables the collission detection. The DIM1 bit enables/disables the TIC bus access. The effect of the individual DIM bits is summarized in table 25. Table 25 IOM(R)-2 Terminal Modes
DIM2 0 0 0 0 1 DIM1 x x 0 1 x DIM0 Characteristics 0 1 x x x
Transparent D-channel, the collission detection is disabled Stop/go bit evaluated for D-channel access handling Last octet of IOM channel 2 used for TIC bus access TIC bus access is disabled Reserved
7.0.7
EXMR- Extended Mode Register
Value after reset: 00H 7 EXMR XFBS XFBS RFBS SRA XCRC RCRC 0 0 ITF RD/WR (23H)
... Transmit FIFO Block Size
0: Block size for the transmit FIFO data is 32 byte 1: Block size for the transmit FIFO data is 16 byte Note: A change of XFBS will take effect after a transmitter command (CMDR.XME, CMDR.XRES, CMDR.XTF) has been written RFBS RFBS Bit6 0 0 ... Receive FIFO Block Size RFBS Block Size Bit5 Receive FIFO 0 1 32 byte 16 byte
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Detalled Register Description RFBS Bit6 1 1 RFBS Block Size Bit5 Receive FIFO 0 1 8 byte 4 byte
Note: A change of RFBS will take effect after a receiver command (CMDR.RMC, CMDR.RRES,) has been written
SRA
... Store Receive Address
0: Receive Address is not stored in the RFIFO 1: Receive Address is stored in the RFIFO XCRC ... Transmit CRC
0: CRC is transmitted 1: CRC is not transmitted RCRC ... Receive CRC
0: CRC is not stored in the RFIFO 1: CRC is stored in the RFIFO ITF ... Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-frames. 0: Idle (continuous '1') 1: Flags (sequence of patterns: `0111 1110') Note: ITF must be set to '0' for power down mode. In applications with D-channel access handling (collision resolution), the only possible inter-frame time fill is idle (continuous '1'). Otherwise the D-channel on the line interface can not be accessed 7.0.8 TIMR - Timer Register
Value after reset: 00H 7 TIMR CNT 5 4 VALUE 0 RD/WR (24H)
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Detalled Register Description CNT ...
CNT together with VALUE determine the time period T2 after which a TIN interrupt will be generated in the normal case: T = CNT x 2.048 sec + T1 with T1 = ( VALUE+1 ) x 0.064 sec The timer can be started by setting the STI-bit in CMDR and will be stopped when a TIN interrupt is generated or the TIMR register is written. Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every expiration of T1. VALUE ... Determines the time period T1 T1 = ( VALUE + 1 ) x 0.064 sec
7.0.9
SAP1 - SAPI1 Register
Value after reset: FCH 7 SAP1 SAPI1 SAPI1 ... SAPI1 value 0 0 MHA WR (25H)
Value of the first programmable Service Access Point Identifier (SAPI) according to the ISDN LAPD protocol. MHA ... Mask High Address
0: The SAPI address of an incoming frame is compared with SAP1, SAP2, SAPG 1: The SAPI address of an incoming frame is compared with SAP1 and SAPG. SAP1 can be masked with SAP2 thereby bit positions of SAP1 are not compared if they are set to '1' in SAP2.
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Detalled Register Description 7.0.10 RBCL - Receive Frame Byte Count Low
Value after reset: 00H 7 RBCL RBC7-0 RBC7 ... Receive Byte Count 0 RBC0 RD (26H)
Eight least significant bits of the total number of bytes in a received message. 7.0.11 SAP2 - SAPI2 Register
Value after reset: FCH 7 SAP2 SAPI2 SAPI2 ... SAPI2 value 0 0 MLA WR (26H)
Value of the second programmable Service Access Point Identifier (SAPI) according to the ISDN LAPD-protocol. MLA 0: 1: ... Mask Low Address The TEI address of an incoming frame is compared with TEI1, TEI2, TEIG The TEI address of an incoming frame is compared with TEI1 and TEIG. TEI1 can be masked with TEI2 thereby bit positions of TEI1 are not compared if they are set to '1' in TEI2
Data Sheet
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Detalled Register Description 7.0.12 RBCH - Receive Frame Byte Count High
Value after reset: 00H. 7 RBCH OV 0 0 ... Overflow 0 OV RBC11 0 RBC8 RD (27H)
A '1' in this bit position indicates a message longer than (212 - 1) = 4095 bytes . RBC11-8 ... Receive Byte Count
Four most significant bits of the total number of bytes in a received message. Note: Normally RBCH and RBCL should be read by the microcontroller after an RMEinterrupt in order to determine the number of bytes to be read from the RFIFO, and the total message length. The contents of the registers are valid only after an RME or RPF interrupt, and remain so until the frame is acknowledged via the RMC bit or RRES. 7.0.13 TEI1 - TEI1 Register 1
Value after reset: FFH 7 TEI1 TEI1 0 EA WR (27H)
TEI1 ... Terminal Endpoint Identifier In all message transfer modes except in transparent modes 0, 1 and extended transparent mode, TEI1 is used for address recognition. In the case of a two-byte address field, it contains the value of the first programmable Terminal Endpoint Identifier according to the ISDN LAPD-protocol. In non-auto-modes with one-byte address field, TEI1 is a command address, according to X.25 LAPB. EA ... Address field Extension bit
This bit is set to '1' according to HDLC/LAPD.
Data Sheet
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Detalled Register Description 7.0.14 RSTA - Receive Status Register
Value after reset: 0EH 7 RSTA VFR VFR RDO CRC RAB SA1 SA0 C/R 0 TA RD (28H)
... Valid Frame
Determines whether a valid frame has been received. The frame is valid (1) or invalid (0). A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag, abort). RDO ... Receive Data Overflow
If RDO=1, at least one byte of the frame has been lost, because it could not be stored in RFIFO. CRC ... CRC Check
The CRC is correct (1) or incorrect (0). RAB ... Receive Message Aborted
The receive message was aborted by the remote station (1), i.e. a sequence of seven 1's was detected before a closing flag. SA1-0 TA ... SAPI Address Identification ... TEI Address Identification
SA1-0 are significant in non-auto-mode with a two-byte address field, as well as in transparent mode 3. TA is significant in all modes except in transparent modes 0 and 1. Two programmable SAPI values (SAP1, SAP2) plus a fixed group SAPI (SAPG of value FC/FEH), and two programmable TEI values (TEI1, TEI2) plus a fixed group TEI (TEIG of value FFH), are available for address comparison. The result of the address comparison is given by SA1-0 and TA, as follows: C/R ... Command/Response
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address) Note: The contents of RSTA corresponds to the last received HDLC frame; it is duplicated into RFIFO for every frame (last byte of frame) Note: If SAP1 and SAP2 contains identical values, the combination 001 will be omitted.
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Detalled Register Description Address Match with SA1 Number of Address Bytes = 1 x x 0 0 0 0 1 1 1 SA0 x x 0 0 1 1 0 0 1 TA 0 1 0 1 0 1 0 1 x 1st Byte TEI2 TEI1 SAP2 SAP2 SAPG SAPG SAP1 SAP1 2nd Byte TEIG TEI2 TEIG TEI1 or TEI2 TEIG TEI1 reserved
Number of address Bytes=2
7.0.15
TEI2 - TEI2 Register
Value after reset: FFH 7 TEI2 TEI2 TEI2 ... Terminal Endpoint Identifier 0 EA WR (28H)
In all message transfer modes except in transparent modes 0, 1 and extended transparent mode, TEI2 is used for address recognition. In the case of a two-byte address field, it contains the value of the second programmable Terminal Endpoint Identifier according of the ISDN LAPD-protocol. In non-auto-modes with one-byte address field, TEI2 is a response address, according to X.25 LAPD. EA ... Address field Extension bit
This bit is to be set to '1' according to HDLC/LAPD.
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Detalled Register Description 7.0.16 TMH -Test Mode Register HDLC
Value after reset: 00H 7 TMH TLP 0 0 0 0 0 0 0 0 TLP RD/WR (29H)
... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming from the layer 1 controller will not be forwarded to the layer 2 controller (see chapter 3.7). Bit 7:1 have always be programmed to '0'. 7.0.17 CIR0 - Command/Indication Receive 0
Value after reset: F3H 7 CIR0 CODR0 CODR0 ... C/I Code 0 Receive CIC0 CIC1 S/G 0 BAS RD (2EH)
Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only after being the same in two consecutive IOM-frames and the previous code has been read from CIR0. CIC0 ... C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is set only when a new code is detected in two consecutive IOM-frames. It is reset by a read of CIR0. CIC1 ... C/I Code 1 Change
A change in the received Command/Indication code in IOM-channel 1 has been recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by a read of CIR0. S/G 1: Stop 0: Go ... Stop/Go Bit Monitoring
Indicates the availability of the D-channel on the line interface.
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Detalled Register Description BAS ... Bus Access Status
Indicates the state of the TIC-bus: 0: The SCOUT itself occupies the D- and C/I-channel 1: Another device occupies the D- and C/I-channel Note: The CODR0 bits are updated every time a new C/I-code is detected in two consecutive IOM-frames. If several consecutive valid new codes are detected and CIR0 is not read, only the first and the last C/I code is made available in CIR0 at the first and second read of that register, respectively. The following CI indications are used:
The
Indication (Downstream) Deactivation Request Power-Up Test Mode Acknowledge Resynchronization Activation Request Activation Request Loop 3 Activation Request Loop 2 Activation Indication
Abbr. Code Remarks DR PU TMA RSY AR ARL 0000 0111 0010 0100 1000 1001 Acknowledge for both SSP and SCP Receiver not synchronous Receiver synchronized Local loop synchronized Remote loop synchronized
ARL2 1010 AI 1100 1101 1110 1111
Activation Indication Loop 3 AIL Activation Indication Loop 2 AIL2 Deactivation Confirmation DC
Local loop activated Remote loop activated Line- and if MODE1.CFS = '1' also lOMinterface are powered down
Data Sheet
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Detalled Register Description 7.0.18 CIX0 - Command/Indication Transmit 0
Value after reset: FEH 7 CIX0 CODX0 CODX0 ... C/I-Code 0 Transmit TBA2 TBA1 TBA0 0 BAC WR (2EH)
Code to be transmitted in the C/I-channel 0. TBA2-0 ... TIC Bus Address
Defines the individual address for the SCOUT on the IOM bus. This address is used to access the C/I- and D-channel on the IOM interface. Note: If only one device is liable to transmit in the C/I- and D-channels of the IOM it should always be given the address value '7'. BAC ... Bus Access Control
Only valid if the TIC-bus feature is enabled (MODE:DIM2-0). If this bit is set, the SCOUT will try to access the TIC-bus to occupy the C/I-channel even if no D-channel frame has to be transmitted. It should be reset when the access has been completed to grant a similar access to other devices transmitting in that IOM-channel. Note: If the TIC-bus address (TBA2-0) is programmed to '7' and is not blocked by another device the SCOUT writes its C/I0 code to IOM continuously. 7.0.19 CIR1 - Command/Indication Receive 1
Value after reset: FCH 7 CIR1 CODR1 CODR1 ... C/I-Code 1 Receive 0 0 0 RD (2FH)
Value of the received Command/Indication code.
Data Sheet
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Detalled Register Description 7.0.20 CIX1 - Command/Indication Transmit 1
Value after reset: FEH 7 CIX1 CODX1 CODX1 ... C/I-Code 1 Transmit CICW 0 CI1E WR (2FH)
Bits 7-2 of C/I-channel 1 CICW ... C/I-Channel Width
CICW selects between a 4 bit ('0') and 6 bit ('1') C/I1 channel width CI1E ... C/I-channel 1 interrupt enable
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled (1) or masked (0). The following CI commands are used. Command (Upstream) Timing Reset Send Single Pulses Send Continuous Pulses Activate Request Activate Request Loop 3 Deactivation Indication Abbr. Code Remarks TIM RES SSP SCP AR ARL Dl 0000 0001 0010 0011 1000 1001 1111 Local analog loop Layer-2 device requires clocks to be activated Statemachine reset AMI coded pulses transmitted at 4 kHz AMI coded pulses transmitted continuously
Data Sheet
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Detalled Register Description 7.1 7.1.1 Transceiver, Interrupt and General Configuration Registers TR_CONF0 - Transceiver Configuration Register
Value after reset: 00H 7 TR_ CONF0 DIS_TR DIS_ TR 0 0 TCM L1SW 0 0 0 LDD RD/WR (30H)
... Disable Transceiver
0: All layer-1 functions are enabled. 1: All layer-1 functions are disabled. The HDLC controller and codec part can still operate via IOM-2. DCL and FSC pins become input. TCM ... T-Channel Mapping
0: T-channel data downstream (UPN --> IOM-2) is mapped onto the S/G-bit (S/G = inverted T-bit) 1: T-channel data downstream (UPN --> IOM-2) is mapped onto the A/B-bit (A/B = T) L1SW ... Enable Layer 1 State Machine in Software
0: Layer 1 state machine of the SCOUT is used 1: Layer 1 state machine is disabled. The functionality can be realized in software. The commands can be written in register TR_CMD and the status read from the TR_STA. LDD ... Level Detection Discard
0: Clock generation after detection of any signal on the line in the power down state 1: No clock generation after detection of any signal on the line in the power down state Note: If an interrupt is generated by the internal level detect circuitry, the microcontroller has to set this bit to '0' for an activation of the line interface.
Data Sheet
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Detalled Register Description 7.1.2 TR_CONF1 - Receiver Configuration Register
Value after reset: 62H 7 TR_ CONF1 RPLL_ INTD 1 EN_ SFSC 0 0 0 1 0 0 RD/WR (31H)
RPLL_INTD
... Receive PLL Integrator Disable (refer to chapter 5.1.1)
0: The integrator function of the receive PLL is enabled 1: The integrator function of the receive PLL is disabled EN_SFSC ... Enable Short FSC
0: No short FSC is generated 1: A short FSC with a pulse length of 1 DCL is generated once per multi-frame (each 8th IOM frame) (refer to chapter 2.3.4) 7.1.3 TR_CONF2 - Transmitter Configuration Register
Value after reset: 00H 7 TR_ CONF2 DIS_TX DIS_ TX 0 0 TRS 0 0 0 0 0 RD/WR (32H)
... Disable Line Driver
The transmitter of the UPN transceiver can be disabled or enabled by setting DIS_TX. This can be used to make the analog loop (Loop3) transparent (DIS_TX = '0') or not (DIS_TX = '1'). 0: Transmitter is enabled 1: Transmitter is disabled TRS ... Transformer Ratio Selection
0: An external transformer of ratio 1:1 is connected to the transceiver line interface. Only useful if 3.3V power supply voltage is applied. 1: An external transformer of ratio 2:1 is connected to the transceiver line interface Only useful if 5V power supply voltage is applied.
Data Sheet
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Detalled Register Description 7.1.4 TR_STA - Transceiver Status Register
Value after reset: 00H 7 TR_ STA RINF RINF 0 RDS RLP FSYN FCV 0 MSYN RD (33H)
... Receiver INFO
00: Received INFO 0 01: Received any signal except INFO 2 or INFO 4 10: Received INFO 2 11: Received INFO 4 RDS ... Running Digital Sum
0: No code violation beyond F- or M-bit 1: At least one code violation beyond F- or M-bit received RLP ... Remote Loop
0: No remote loop is activated 1: The remote loop (Loop2) is activated by the S-bit of the UPN multiframe. The received data is looped back to the UPN interface. The D-channel information is transparently forwarded to the downstream IOM-2 D-channel. The downstream B-channel information is not transparent and fixed to 'FFH'. FSYN ... Frame Synchronization State
0: The UPN receiver has not synchronized or has lost synchronization to the framing bit F 1: The UPN receiver has synchronized to the framing bit F FCV ... F-Bit Code Violation
0: No code violation in the F-bit has been detected 1: A code violation in the F-bit has been detected MSYN ... Multiframe Synchronous
0: The UPN receiver has not synchronized or has lost synchronization to the UPN multiframe 1: The UPN receiver has synchronized to the UPN multiframe
Data Sheet
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Detalled Register Description 7.1.5 TR_CMD - Transceiver Command Register
Value after reset: 00H 7 TR_ CMD XINF 0 0 PD LP_A 0 0 RD/WR (34H)
Normally the signals in this register are generated by the layer 1 state machine. If the internal layer 1 state machine is disabled (bit L1SW in TR_CONF = '1') this register can be written by the microcontroller. XINF ... Transmit INFO
000: Transmit INFO 0 001: Transmit INFO 1W 010: Transmit INFO 1 011: Transmit INFO 3 100: Send continuos 192 kHz pulses (Test Mode 2) 101: Send single 4 kHz pulses (Test Mode 1) 11x: reserved PD ... Power Down
0: Transceiver in operational mode 1: Transceiver in power down mode. From the analog part only the level detector is active. Additionally no clocks are provided and the complete digital part of the transceiver is inactive if the CFS bit (see chapter 7.1.10) is set to '1'. LP_A ... Loop Analog
The setting of this bit corresponds to the C/I command ARL. 0: Analog loop is open 1: Analog loop is closed
Data Sheet
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Detalled Register Description 7.1.6 ISTATR - Interrupt Status Register Transceiver
Value after reset: 00H 7 ISTATR 0 x x x LD RIC 0 0 0 RD (38H)
For all interrupts in the ISTATR register following logical states are defined: 0: Interrupt is not activated 1: Interrupt is activated x LD ... Reserved ... Level Detection
Any receive signal has been detected on the line RIC ... Receiver INFO Change
Any bit of register TR_STA has changed. This bit is reset by reading this register 7.1.7 MASKTR - Mask Transceiver Interrupt
Value after reset: 7FH 7 MASKTR 0 1 1 1 LD RIC 1 0 1 RD/WR (39H)
0: The transceiver interrupts LD and RIC are enabled 1: The transceiver interrupts LD and RIC are disabled
Data Sheet
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Detalled Register Description 7.1.8 ISTA - Interrupt Status Register
Value after reset: 01H 7 ISTA 0 ST CIC TIN 0 WOV TRAN MOS HDLC RD (3CH)
For all interrupts in the ISTA register following logical states are applied: 0: Interrupt is not activated 1: Interrupt is activated ST ... Synchronous Transfer
When programmed (STI register), this interrupt is generated to enable the microcontroller to lock on to the IOM timing, for synchronous transfers. CIC ... C/I Channel Change
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can be read from CIR0 or CIR1. TIN ... Timer Interrupt
The internal timer and repeat counter has expired (see TIMR register). WOV ... Watchdog Timer Overflow
Used only if terminal specific functions are enabled (MODE.TSF=1). Signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits WTC1 and WTC2 (ADF1 register) in the correct manner. A reset pulse has been generated by the SCOUT. TRAN ... Transceiver Interrupt
An interrupt originated in the transceiver interrupt status register (ISTATR) has been recognized. MOS ... MONITOR Status
A change in the MONITOR Status Register (MOSR) has occurred. HDLC ... HDLC Interrupt
An interrupt originated in the HDLC interrupt sources has been recognized. Note: A read of the ISTA register clears only the TIN and WOV interrupts. The other interrupts are cleared by reading the corresponding status register
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Detalled Register Description 7.1.9 MASK - Mask Register
Value after reset: 7FH 7 MASK 0 ST CIC TIN 0 WOV TRAN MOS HDLC WR (3CH)
For the MASK register following logical states are applied: 0: Interrupt is not masked 1: Interrupt is masked Each interrupt source in the ISTA register can be selectively masked by setting to '1' the corresponding bit in MASK. Masked interrupt status bits are not indicated when ISTA is read. Instead, they remain internally stored and pending, until the mask bit is reset to '0'. Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding mask bit in MASK is active, but no interrupt is generated. 7.1.10 MODE1 - Mode1 Register
Value after reset: 00H 7 MODE1 MCLK MCLK CDS WTC1 WTC2 CFS 0 RSS2 RSS1 RD/WR (3DH)
... Master Clock Frequency
The Master Clock Frequency bits control the microcontroller clock output corresponding following table.
Bit 7 Bit 6 MCLK frequency MCLK frequency with with MODE1.CDS = '0' MODE1.CDS = '1' 0 0 1 1 0 1 0 1 3.84 MHz 0.96 MHz 7.68 MHz disabled 7.68 MHz 1.92 MHz 15.36 MHz disabled
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Detalled Register Description CDS ... Clock Divider Selection
0: The 15.36 MHz oscillator clock divided by two is input to the MCLK prescaler 1: The 15.36 MHz oscillator clock is input to the MCLK prescaler. WTC1, 2 ... Watchdog Timer Control 1, 2
If the watchdog timer is enabled (RSS = '11') the microcontroller has to program the WTC1 and WTC2 bit within each time period of 128 ms in the following sequence: WTC1 1. 2. (See chapter 6.1). CFS ... Configuration Select 1 0 WTC2 0 1
This bit determines clock relations and recovery on the line and IOM interfaces 0: The IOM interface clock and frame signals are always active, "Power Down" state included. The states "Power Down" and "Power Up" are thus functionally identical except for the indication: PD = 1111 and PU = 0111. With the C/I command Timing (TIM) the microcontroller can enforce the "Power Up" state. With C/I command Deactivation Indication (DI) the "Power Down" state is reached again. It is also possible to activate the line Interface directly with the C/I command Activate Request (AR) without the TIM command. 1: The IOM interface clock and frame signals are normally inactive ("Power Down"). For activating the IOM-2 clocks the "Power Up" state can be induced by software (SPU-bit in SPCR register) or by resetting again CFS. After that the line interface can be activated with the C/I command Activate Request (AR ). The "Power Down" state can be reached again with the C/I command Deactivation Indication (DI). Note:After reset the IOM interface is always active. To reach the "Power Down" state the CFS-bit has to be set.
Data Sheet
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Detalled Register Description .RSS2, RSS1 ... Reset Source Selection 2,1
The reset sources and the SDS2 functionality for the RSTO/SDS2 output pin can be selected according to the table below. RSS2 RSS1 Bit 1 Bit 0 0 0 1 1 0 1 0 1 C/I Code Change --EAW --Watchdog Timer ---SDS2 Functionality --
x
---
x
--
x
--
x
For RSS = '00' no reset is generated at pin RSTO/SDS2. For RSS = '01' a serial data strobe is output at pin RSTO/SDS2 (see chapter 2.2.3). For RSS = '10' an External Awake or a change in the downstream C/I0 channel generates a reset of 125 s t 250 s pulse length at the pin RSTO (see chapter 6.1). For RSS = '11' the watchdog function is enabled (see chapter 6.1). A hardware reset or a reset generated by the undervoltage detection is always output at pin RSTO/SDS2. After a reset pulse and the corresponding interrupt (WOV or CIC) have been generated by the SCOUT the actual reset source can be read from the ISTA. 7.1.11 MODE2 - Mode2 Register
Value after reset: 00H 7 MODE2 PPSDX 0 0 0 0 0 DREF 0 0 PPSDX RD/WR (3EH)
... Push/Pull Output for SDX
0: The SDX pin has open drain characteristic 1: The SDX pin has push/pull characteristic DREF ... Disable References
0: Reference voltages and currents are enabled. 1: Reference voltages and currents are disabled.
Data Sheet
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Detalled Register Description 7.1.12 ID - Identification Register
Value after reset: 0xH 7 ID DESIGN 0 0 ... Design Number DESIGN 0 RD (3FH)
The design number (DESIGN) allows to identify different hardware designs of the SCOUT by software. 000000: SCOUT-P V1.3 PSB 21391 000001: SCOUT-PX V1.3 PSB 21393 7.1.13 SRES - Software Reset Register
Value after reset: 00H 7 SRES 0 0 0 RES_ RES_ RES_ RES_ RES_ RES_ CPLL MON HDLC IOM TR CO WR (3FH)
RES_xx
... Reset_xx
0: Deactivates the reset of the functional block xx 1: Activates the reset of the functional block xx The reset state is activated as long as the bit is set to '1' Meaning of xx: CPLL: MON: HDLC: IOM: TR: CO: Codec PLL Monitor handler HDLC controller, IOM Handler, Transceiver, Codec
Data Sheet
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Detalled Register Description 7.2 7.2.1 IOM-2 and MONITOR Handler CDAxy - Controller Data Access Register xy
Value after reset: See table below 7 CDAxy Controller Data Access Register 0 RD/WR (40H-43H) Data register CDAxy which can be accessed from the controller. Register CDA10 CDA11 CDA20 CDA21 Value after Reset FFH FFH FFH FFH Register Address 40H 41H 42H 43H
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Detalled Register Description 7.2.2 XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
Value after reset: See table below 7 XXX_ TSDPxy DPS 0 0 0 TSS 0 RD/WR (44H-4DH)
Register CDA_TSDP10 CDA_TSDP11 CDA_TSDP20 CDA_TSDP21 CO_TSDP10 CO_TSDP11 CO_TSDP20 CO_TSDP21 TR_TSDP_B1 TR_TSDP_B2
Value after Reset 00H ( = output on B1-DD) 01H ( = output on B2-DD) 80H ( = output on B1-DU) 81H ( = output on B2-DU) 80H ( = output on B1-DU) 81H ( = output on B2-DU) 81H ( = output on B2-DU) 85H ( = output on IC2-DU) 00H ( = output on B1-DD) 01H ( = output on B2-DD)
Register Address 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH
This register determines the time slots and the data ports on the IOM-2 Interface for the data channels xy of the functional units XXX (Controller Data Access (CDA), Codec (CO) and Transceiver (TR)). DPS ... Data Port Selection
0: The data channel xy of the functional unit XXX is output on DD. The data channel xy of the functional unit XXX is input from DU. 1: The data channel xy of the functional unit XXX is output on DU. The data channel xy of the functional unit XXX is input from DD. Note: For the CDA (controller data access) data the input is determined by the CDA_CRx.SWAP bit. If SWAP = '0' the input for the CDAxy data is vice versa to the output setting for CDAxy. If the SWAP = '1' the input from CDAx0 is vice versa to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output setting of CDAx0. See controller data access description in chapter 2.2.2.1
Data Sheet
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Detalled Register Description TSS ... Timeslot Selection
Selects one of the 12 timeslots from 0...11 on the IOM-2 interface for the data channels. 7.2.3 CDAx_CR - Control Register Controller Data Access CH1x
Value after reset: See table below 7 CDAx_ CR 0 0 EN_ TBM 0 EN_I1 EN_I0 EN_O1 EN_O0 SWAP RD/WR (4EH-4FH)
Register CDA1_CR CDA2_CR EN_TBM
Value after Reset 00H 00H
Register Address 4EH 4FH
... Enable TIC Bus Monitoring
0: The TIC bus monitoring is disabled 1: The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register must be set to 08H for monitoring from DU or 88H for monitoring from DD respectively. EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1
0: The input of the CDAx0, CDAx1 register is disabled 1: The input of the CDAx0, CDAx1 register is enabled EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1 0: The output of the CDAx0, CDAx1 register is disabled 1: The output of the CDAx0, CDAx1 register is enabled SWAP ... Swap Inputs
0: The time slot and data port for the input of the CDAxy register is defined by its own TSDPxy register. The data port for the CDAxy input is vice versa to the output setting for CDAxy. 1: The input (time slot and data port) of the CDAx0 is defined by the TSDP register of CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to CDAx0. The outputs are not affected by the SWAP bit.
Data Sheet
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Detalled Register Description 7.2.4 CO_CR - Control Register Codec Data
Value after reset: 00H 7 CO_CR 0 0 0 0 EN 21 EN 20 EN 11 0 EN 10 RD/WR (50H)
EN21 EN20 EN11 EN10
... Enable codec channel 21 ... Enable codec channel 20 ... Enable codec channel 11 ... Enable codec channel 10
0: The codec data channel xy is disabled 1: The codec data channel xy is enabled 7.2.5 TR_CR - Control Register Transceiver Data
Value after reset: 3EH 7 TR_CR 0 0 EN_ D EN_ B2R EN_ B1R EN_ B2X EN_ B1X 0 0 RD/WR (51H)
EN_D EN_B2R EN_B1R EN_B2X EN_B1X
... Enable D-Channel Data ... Enable B2 Data received from IOM ... Enable B1 Data received from IOM ... Enable B2 Data to be transmitted to IOM ... Enable B1 Data to be transmitted to IOM
0: The transceiver data _xxx is disabled 1: The transceiver data _xxx is enabled
Data Sheet
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Detalled Register Description 7.2.6 HCI_CR - Control Register for HDLC and CI1 Data
Value after reset: A0H 7 HCI_CR DPS_ CI1 EN_ CI1 EN_ D EN_ B2H EN_ B1H 0 0 0 0 RD/WR (52H)
DPS_CI1
... Data Port Selection CI1 Data
0: The CI1 data is output on DD and input from DU 1: The CI1 data is output on DU and input from DD EN_CI1 EN_D EN_B2H EN_B1H ... Enable CI1 Data ... Enable D-Channel Data ... Enable HDLC B2 Data ... Enable HDLC B1 Data
0: The HDLC (D, B1, B2) and CI1 data is disabled 1: The HDLC (D, B1, B2) and CI1 data is enabled 7.2.7 MON_CR - Control Register Monitor Data
Value after reset: 40H 7 MON_CR DPS EN_ MON 0 0 0 0 0 MCS RD/WR (53H)
DPS
... Data Port Selection
0: The Monitor data is output on DD and input from DU 1: The Monitor data is output on DU and input from DD EN_MON ... Enable Output
0: The Monitor data input and output is disabled 1: The Monitor data input and output is enabled MCS ... MONITOR Channel Selection
00: The MONITOR data is output on MON0 01: The MONITOR data is output on MON1 10: The MONITOR data is output on MON2 11: Not defined
Data Sheet
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Detalled Register Description 7.2.8 SDSx_CR - Control Register Serial Data Strobe x
Value after reset: 00H 7 SDSx_CR ENS_ ENS_ ENS_ TSS TSS+1 TSS+3 0 TSS 0 RD/WR (54H-55H)
Register SDS1_CR SDS2_CR
Value after Reset 00H 00H
Register Address 54H 55FH
Note: The SDS2_CR register is only applicable if a serial data strobe functionality is selected (MODE1.RSS = '01') for the pin RSTO/SDS2 ENS_TSS ENS_TSS+1 ... Enable Serial Data Strobe of timeslot TS ... Enable Serial Data Strobe of timeslot TS+1
0: The serial data strobe or bit clock on SDSx for TS, TS+1 is disabled 1: The serial data strobe or bit clock on SDSx for TS, TS+1 is enabled ENS_TSS+3 ... Enable Serial Data Strobe of timeslot TS+3 (D-Channel)
0: The serial data strobe or bit clock on SDSx for the D-channel (bit7, 6) of TS+3 is disabled 1: The serial data strobe or bit clock on SDSx for the D-channel (bit7, 6) of TS+3 is enabled TSS ... Timeslot Selection
Selects one of 12 timeslots on the IOM-2 interface (with respect to FSC) during which SDSx is active. The data strobe signal allows standard data devices to access a programmable channel.
Data Sheet
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Detalled Register Description 7.2.9 IOM_CR - Control Register IOM Data
Value after reset: 00H 7 IOM_CR SPU 0 0 TIC_ DIS EN_ BCL CLKM DIS_ OD 0 DIS_ RD/WR (56H) IOM
SPU
... Software Power UP
0: The DU line is normally used for transmitting data 1: Setting this bit to '1' will pull the DU line to low. This will enforce connected layer 1 devices to deliver IOM-clocking. After a subsequent CIC-interrupt (C/I-code change; ISTA) and reception of the C/I-code "PU" (Power Up indication in TE-mode) the microcontroller writes an AR or TIM command as C/I-code in the CIX0-register, resets the SPU bit and wait for the following CIC-interrupt. TIC_DIS ... TIC Bus Disable
0: The last octet of the last IOM time slot (TS 11) is used as TIC bus 1: The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used as every time slot. EN_BCL ... Enable Bit Clock BCL
0: The BCL clock is disabled 1: The BCL clock is enabled CLKM ... Clock Mode
If the transceiver is disabled (DIS_TR = '1') the DCL from the IOM-2 interface is an input. With 0: A double clock per bit is expected 1: A single clock per bit is expected DIS_OD ... Open Drain
0: IOM outputs are open drain driver 1: IOM outputs are push pull driver
Data Sheet
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Detalled Register Description DIS_IOM ... Disable IOM
DIS_IOM should be set to '1' if external devices connected to the IOM interface should be "disconnected" e.g. for power saving purposes or for not disturbing the internal IOM connection between layer 1 and layer 2. However, the SCOUT internal operation between transceiver, B-channel and D-channel controller is independent of the DIS_IOM bit. 0: The IOM interface is enabled 1: The IOM interface is disabled (high impedance) 7.2.10 MCDA - Monitoring CDA Bits
Value after reset: FFH 7 MCDA MCDA21 Bit7 MCDAxy Bit6 MCDA20 Bit7 Bit6 MCDA11 Bit7 Bit6 0 MCDA10 Bit7 Bit6 RD (57H)
... Monitoring CDAxy Bits
Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register. This can be used for monitoring the D-channel bits on DU and DD and the 'Echo bits' on the TIC bus with the same register
Data Sheet
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Detalled Register Description 7.2.11 STI - Synchronous Transfer Interrupt
Value after reset: 00H 7 STI STOV STOV STOV STOV 21 20 11 10 STI 21 STI 20 STI 11 0 STI 10 RD (58H)
For all interrupts in the STI register following logical states are applied: 0: Interrupt is not activated 1: Interrupt is aestivated STOVxy ... Synchronous Transfer Overflow Interrupt
Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one (for DPS='0') or zero (for DPS='1') BCL clocks before the time slot which is selected for the STOV. STIxy ... Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the Synchronous Transfer Interrupt STIxy is generated two (for DPS='0') or one (for DPS='1') BCL clock after the selected time slot (TSDPxy.TSS). Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and receive/transmit operations. One BCL clock is equivalent to two DCL clocks.
Data Sheet
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Detalled Register Description 7.2.12 ASTI - Acknowledge Synchronous Transfer Interrupt
Value after reset: 00H 7 ASTI 0 0 0 0 ACK 21 ACK 20 ACK 11 0 ACK 10 WR (58H)
ACKxy
... Acknowledge Synchronous Transfer Interrupt
After a STIxy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ACKxy bit. 0: No activity is initiated 1: Sets the acknowledge bit ACKxy for a STIxy interrupt 7.2.13 MSTI - Mask Synchronous Transfer Interrupt
Value after reset: FFH 7 MSTI STOV STOV STOV STOV 21 20 11 10 STI 21 STI 20 STI 11 0 STI 10 RD/WR (59H)
For the MSTI register following logical states are applied: 0: Interrupt is not masked 1: Interrupt is masked STOVxy ... Synchronous Transfer Overflow for STIxy
By masking the STOV bits the number and time of the STOV interrupts for a certain enabled STIxy interrupt can be controlled. For an enabled STIxy the own STOVxy is generated when the STOVxy is enabled (MSTI.STIxy and MSTI.STOVxy = '0'). Additionally all other STOV interrupts of which the corresponding STI is disabled (MSTI.STI = '1' and MSTI.STOV = '0') are generated. STIxy ... Synchronous Transfer Interrupt xy
The STIxy interrupts can be masked by setting the corresponding mask bit to '1'. For a masked STIxy no STOV interrupt is generated.
Data Sheet
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Detalled Register Description 7.2.14 SDS_CONF - Configuration Register for Serial Data Strobes
Value after reset: 00H 7 SDS_ CONF SDSx_BCL 0 0 0 0 0 0 0 SDS2_ SDS1_ RD/WR (5AH) BCL BCL
... Enable IOM Bit Clock for SDSx
0: The serial data strobe is generated in the programmed timeslot (see chapter 7.2.8). 1: The IOM bit clock is generated in the programmed timeslot (see chapter 7.2.8 and 2.2.3). 7.2.15 MOR - MONITOR Receive Channel
Value after reset: 00H 7 MOR 0 RD (5CH)
Contains the MONITOR data received in the IOM-2 MONITOR channel according to the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by setting the monitor channel select bit MON_CR.MCS. 7.2.16 MOX - MONITOR Transmit Channel
Value after reset: FFH 7 MOX 0 WR (5CH)
Contains the MONITOR data to be transmitted in IOM-2 MONITOR channel according to the MONITOR channel protocol.The MONITOR channel (0,1,2) can be selected by setting the monitor channel select bit MON_CR.MCS
Data Sheet
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Detalled Register Description 7.2.17 MOSR - MONITOR Interrupt Status Register
Value after reset: 00H 7 MOSR MDR MER MDA MDR MER MDA MAB 0 0 0 0 0 RD (5DH)
... MONITOR channel Data Received ... MONITOR channel End of Reception ... MONITOR channel Data Acknowledged
The remote end has acknowledged the MONITOR byte being transmitted. MAB ... MONITOR channel Data Abort
Data Sheet
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Detalled Register Description 7.2.18 MOCR - MONITOR Control Register
Value after reset: 00H 7 MOCR MRE MRE MRC MIE MXC 0 0 0 0 0 RD/WR (5EH)
... MONITOR Receive Interrupt Enable
0: MONITOR interrupt status MDR generation is masked 1: MONITOR interrupt status MDR generation is enabled MRC ... MR Bit Control:
Determines the value of the MR bit: 0: MR is always '1'. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRE = 1). 1: MR is internally controlled according to the MONITOR channel protocol. In addition, the MDR interrupt is enabled for all received bytes according to the MONITOR channel protocol (if MRE = 1). MIE ... MONITOR Interrupt Enable
MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0). MXC ... MX Bit Control
Determines the value of the MX bit: 0: The MX bit is always '1'. 1: The MX bit is internally controlled according to the MONITOR channel protocol.
Data Sheet
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Detalled Register Description 7.2.19 MSTA - MONITOR Status Register
Value after reset: 00H 7 MSTA MAC 0 0 0 0 0 MAC 0 0 TOUT RD (5FH)
... MONITOR Transmit Channel Active
The data transmission in the MONITOR channel is in progress TOUT ... Time-Out
Read-back value of the TOUT bit 7.2.20 MCONF - MONITOR Configuration Register 7 MCONF TOUT 0 0 0 0 0 0 0 0 TOUT WR (5FH)
Value after reset: 00H
... Time-Out
0: The monitor time-out function is disabled 1: The monitor time-out function is enabled
Data Sheet
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Detalled Register Description 7.3 7.3.1 Codec Configuration Registers General Configuration Register (GCR)
Value after reset: 00H 7 GCR SP SP AGCX AGCR MGCR CME PU 0 ATT2R ATT1R RD/WR (60H)
... Speakerphone
0: Speakerphone support disabled 1: Speakerphone support enabled AGCX ... Automatic Gain Control Transmit
0: Automatic gain control disabled 1: Automatic gain control enabled; only if speakerphone support is enabled (SP=1) AGCR ... Automatic Gain Control Receive
0: Automatic gain control disabled 1: Automatic gain control enabled; only if speakerphone support is enabled (SP=1) MGCR ... Modified Gain Control Receive
0: AGCR starts regulation up and down after speech was detected two times 1: AGCR starts regulation down of the attenuation immediately, regulation up is done after speech was detected two times CME ... Controlled Monitoring Enable (GCR.SP = '1')
0: Controlled monitoring disabled 1: Controlled monitoring enabled. ALS attenuation is fixed to the value determined by the ATCR.CMAS setting Note: If transmit speech is detected and LSC > -9.5 dB, the ALS programming is fixed to -9.5 dB PU ... Power Up
0: The codec is in standby mode (power-down); all registers and the coefficient RAM contents are saved and all interface functions are available 1: The codec is in normal operation mode (power-up)
Data Sheet
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Detalled Register Description ATT2R ATT1R ... Attenuation of the Receive Channel related to Transmit Channel 2 ... Attenuation of the Receive Channel related to Transmit Channel 1
0: Attenuation value for the conferencing loop is 0 dB 1: Attenuation value for the conferencing loop loaded from CRAM 7.3.2 Programmable Filter Configuration Register (PFCR) 0 GZ FX PGZ FR DHPR DHPX RD/WR (61H)
Value after reset: 00H 7 PFCR GX GX GR
... Transmit Gain
0: Gain set to 0 dB 1: Gain coefficients loaded from CRAM GR ... Receive Gain
0: Gain set to 0 dB 1: Gain coefficients loaded from CRAM GZ ... Sidetone Gain
0: Gain set to - dB 1: Gain coefficients loaded from CRAM FX ... Transmit Frequency Correction Filter
0: Filter is bypassed 1: Filter coefficients loaded from CRAM PGZ ... Position Sidetone Gain
0: Tap of the sidetone signal is before the AGC/GHX stage 1: Tap of the sidetone signal is after the AGC/GHX stage FR ... Receive Frequency Correction Filter
0: Filter is bypassed 1: Filter coefficients loaded from CRAM DHPR ... Disable High-Pass Receive (50/60 Hz filter)
0: Filter enabled 1: Filter disabled
Data Sheet
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Detalled Register Description DHPX ... Disable High-Pass Transmit (50/60 Hz filter)
0: Filter enabled 1: Filter disabled 7.3.3 Tone Generator Configuration Register (TGCR) 0 ETF PT SEQ TM SM SQTR RD/WR (62H)
Value after reset: 00H 7 TGCR ET ET DT
... Enable Tone Generator
0: Tone generator is disabled 1: Tone generator is enabled; frequency and gain coefficients loaded from CRAM DT ... Dual Tone Mode
0: Dual tone mode is disabled 1: Dual tone mode is enabled; the output of signal generator FD is added to the tone signal which is determined by TM and SEQ; dual tone mode is only available if TGSR.DTMF = '0' ETF ... Enable Tone Filter
0: Tone filter is by-passed 1: Tone filter is enabled; filter coefficients loaded from CRAM PT ... Pulsed Tone
0: Pulsed tone is disabled 1: Pulsed tone is enabled; time coefficients loaded from CRAM SEQ ... Sequence Generator
0: Sequence generator is disabled, a continuous tone signal is generated 1: Sequence generator is enabled; time coefficients loaded from CRAM TM ... Tone Mode
0: Two-tone sequence is activated when sequence generator is enabled with SEQ = '1' otherwise a continuous signal (F1, G1) is generated 1: Three-tone sequence is activated when sequence generator is enabled with SEQ = '1' otherwise a continuous signal (F2, G2) is generated; three-tone sequence is only available if TGSR.DTMF = '0'
Data Sheet
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Detalled Register Description SM ... Stop Mode
0: Automatic stop mode is disabled 1: Automatic stop mode is enabled; two and three tone ring gets turned off after the sequence is completed SQTR ... Square/Trapezoid Waveform
0: Trapezoid shaped signal is enabled; only available if tone ringing via loudspeaker is disabled with TGSR.TRL = '0' 1: Square-wave signal is enabled 7.3.4 Tone Generator Switch Register (TGSR) 0 0 TRR DTMF TRX 0 0 RD/WR (63H)
Value after reset: 00H 7 TGSR TRL 0 TRL
... Tone Ringing via Loudspeaker
0: Ringing signal is not output directly to the loudspeaker pins 1: Ringing signal (square) is output directly to the loudspeaker pins LSP/LSN TRR ... Tone Ringing Receive
0: Tone signal for receive direction is disabled 1: Tone signal for receive direction is enabled DTMF ... DTMF Mode
0: DTMF mode is disabled 1: DTMF mode is enabled TRX ... Tone Ringing Transmit
0: Tone generator for transmit direction is disabled 1: Tone generator for transmit direction is enabled
Data Sheet
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Detalled Register Description 7.3.5 AFE Configuration Register (ACR) 0 0 SEM DHOP DHON DLSP DLSN RD/WR (64H)
Value after reset: 00H 7 ACR SEM 0 0
... Single Ended Mode (only effective if DLSP and/or DLSN='1')
0: LSP and/or LSN amplifiers are in power down and grounded internally for single ended mode 1: LSP and/or LSN amplifiers are in power down (high impedance) DHOP ... Disable HOP Amplifier
0: HOP amplifier in normal mode 1: Disable HOP amplifier (power down, output high impedance) DHON ... Disable HON Amplifier
0: HON amplifier in normal mode 1: Disable HON amplifier (power down, output high impedance) DLSP ... Disable LSP Amplifier
0: LSP amplifier in normal mode 1: Disable LSP amplifier controlled by SEM setting DLSN ... Disable LSN Amplifier
0: LSN amplifier in normal mode 1: Disable LSN amplifier controlled by SEM setting
Data Sheet
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Detalled Register Description 7.3.6 AFE Transmit Configuration Register (ATCR) 0 MIC 0 CMAS AIMX RD/WR (65H)
Value after reset: 00H 7 ATCR MIC
... Microphone Amplifier (AMI) Control Bit 7 6 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 5 0 0 1 1 0 0 1 1 0 1 4 0 1 0 1 0 1 0 1 0 1 Selected Mode AMI and PREFI is in power-down mode 0 dB amplification 6 dB amplification 12 dB amplification 18 dB amplification 24 dB amplification 30 dB amplification 36 dB amplification 42 dB amplification bypass mode, reserved for internal tests
CMAS
... Controlled Monitoring Attenuation Select
0: In controlled monitoring mode (GCR.CME = '1') the lower ALS setting is -9.5dB 1: In controlled monitoring mode (GCR.CME = '1') the lower ALS setting is -21.5dB AIMX ... Analog Input Multiplexer Bit 1 0 0 0 1 1 0 1 0 1 Selected Input AMI is connected to the pins MIP1/MIN1 (differential input) AMI is connected to the pins MIP2/MIN2 (differential input) AMI is connected to the pin AXI (single-ended input) not used
Data Sheet
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Detalled Register Description 7.3.7 AFE Receive Configuration Register (ARCR) 0 HOC LSC RD/WR (66H)
Value after reset: 00H 7 ARCR HOC
... Handset Output Amplifier (AHO) Control Bit 3 2 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 Selected Mode AHO is in power-down mode 2.5 dB amplification - 0.5 dB amplification - 3.5 dB amplification - 6.5 dB amplification - 9.5 dB amplification - 12.5 dB amplification - 15.5 dB amplification - 18.5 dB amplification - 21.5 dB amplification bypass mode, reserved for internal tests only
LSC
... Loudspeaker Amplifier (ALS) Control Bit 3 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selected Mode ALS is in power-down mode 11.5 dB amplification 8.5 dB amplification 5.5 dB amplification 2.5 dB amplification - 0.5 dB amplification - 3.5 dB amplification - 6.5 dB amplification - 9.5 dB amplification - 12.5 dB amplification - 15.5 dB amplification - 18.5 dB amplification - 21.5 dB amplification - 24.5 dB amplification (only for TGSR.TRL = '1') - 27.5 dB amplification (only for TGSR.TRL = '1') bypass mode, reserved for internal tests only
Data Sheet
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Detalled Register Description 7.3.8 Data Format Register (DFR) 0 DF2X DF1R DF1X RD/WR (67H)
Value after reset: 00H 7 DFR DFxR Bit 7,3 0 0 1 1 DF2R
... Data Format CHx Receive (CHxR) Bit Data Format CHxR Codec Voice Data Register 6,2 0 1 0 1 PCM A-Law PCM -Law 8-bit linear mode 16-bit linear mode COx0R COx0R COx0R (|sign 15...9| of the internal 16 bit word) COx0R (MSB) (|sign 15...9| of the internal 16 bit word) COx1R (LSB) (|8...1| of the internal 16 bit word)
DFxX Bit 5,1 0 0 1 1
... Data Format CHx Transmit (CHxX) Bit Data Format CHxR Codec Data Register 4,0 0 1 0 1 PCM A-Law PCM -Law 8-bit linear mode 16-bit linear mode COx0X COx0X COx0X (|sign 15...9| of the internal 16 bit word) COx0X (MSB) (|sign 15...9| of the internal 16 bit word) COx1X (LSB) (|8...1| of the internal 16 bit word)
The small letter 'x' is a variable for channel 2 or 1.
Data Sheet
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Detalled Register Description 7.3.9 Data Source Selection Register (DSSR)
Value after reset: 00H 7 DSSR DSSR DSSR ENX2 ENX1 DSS2X 0 DSS1X RD/WR (68H)
... Data Source Selection Receive Bit7 6 0 0 1 1 0 1 0 1 idle CH1R CH2R CH1R+CH2R
ENX2 ENX1
... Enable Transmit CH2 ... Enable Transmit CH1
0: Codec transmit data in CH2/CH1 disabled 1: Codec transmit data in CH2/CH1 enabled DSS2X ... Data Source Selection CH2X Bit3 2 0 0 1 1 DSS1X 0 1 0 1 idle code is transmitted XDAT is transmitted CH1R XDAT+ CH1R is transmitted
... Data Source Selection CH1X Bit1 0 0 0 1 1 0 1 0 1 idle code is transmitted XDAT is transmitted CH2R XDAT+ CH2R is transmitted
Data Sheet
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Detalled Register Description 7.3.10 Extended Configuration (XCR) and Status (XSR) Register
Extended Status Register (XSR) If MAAR in the XCR register is set to '0': Value after reset: 00H 7 XSR PGCR PGCR PGCX ERA 0 0 0
0 SPST RD (69H)
... Position of Gain Control Receive (see figure 62)
Read-back of the programmed value PGCX ... Position of Gain Control Transmit (see figure 62)
Read-back of the programmed value ERA ... Enhanced Reverse Attenuation
Read-back of the programmed value SPST ... Speakerphone State Bit 1 0 0 0 1 1 0 1 0 1 Description Speakerphone is in receive mode Speakerphone is in idle mode (reached via receive mode) Speakerphone is in transmit mode Speakerphone is in idle mode (reached via transmit mode)
If MAAR in the XCR register is set to '1': Value after reset: 00H 7 XSR Value of the Momentary AGC Attenuation 0 RD (69H)
Extended Configuration Register (XCR) Value after reset: 00H 7 XCR
Data Sheet
0 0 0
219
PGCR PGCX ERA
0
0
MAAR
WR (69H)
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Detalled Register Description PGCR ... Position of Gain Control Receive (see figure 62)
0: In front of the speech detector 1: Behind the speech detector PGCX ... Position of Gain Control Transmit (see figure 62)
0: Behind the speech detector 1: In front of the speech detector ERA ... Enhanced Reverse Attenuation
0: Standard reverse attenuation in receive direction 1: Enhanced reverse attenuation in receive direction MAAR ... Monitoring AGC Attenuation Receive
0: The monitoring of the AGC attenuation receive in the XSR register is disabled. XSR contains the read-back values of XCR register (bit 7:2) and the speakerphone states. 1: The monitoring of the AGC attenuation receive in the XSR register is enabled. The momentary AGC attenuation can be accessed directly by the microcontroller via XSR register. 7.3.11 Mask Channel x Register (MASKxR)
Value after reset: 00H 7 MASKxR MASKx 0 MPx RD/WR channel 1: 6AH channel 2: 6BH MASKx ... Mask Channel x
The codec data in channel 1 (CH1X, CH1R) or channel 2 (CH2X,CH2R) respectively is masked with these 6 register bits. The position of this 6 bit mask on the 8 or 16 bit value respectively is determined by the MPx bits. If a mask bit is set to '1' the data in the corresponding bit position is masked and thus always a '1'. With a '0' the data passes unchanged.
Data Sheet
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Detalled Register Description MPx ... Mask Position of Channel x Bit 1 0 0 0 1 1 7.3.12 0 1 0 1 Description Bit 5...0 of the codec data register CHx0 is masked with MASKx Bit 7...2 of the codec data register CHx0 is masked with MASKx Bit 5...0 of the codec data register CHx1 is masked with MASKx Bit 7...2 of the codec data register CHx1 is masked with MASKx
Test Function Configuration Register (TFCR) 0 ALTF DLTF RD/WR (6CH)
Value after reset: 00H 7 TFCR ALTF 0 0
... Analog Loop and Test Functions Bit 5 4 0 0 0 0 1 0 0 1 1 X 3 0 1 0 1 X Test Function NOT: ALF: ALC: ALN: No Test Mode Analog Loop via Front End Analog Loop via Converter Analog Loop via Noise Shaper
Reserved
DLTF
... Digital Loop and Test Functions Bit 2 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 X Test Function NOT: IDR: DLN: DLS: DLP1: DLP2: No Test Mode Initialize DRAM Digital Loop via Noise Shaper Digital Loop via Signal Processor Digital Loop via codec part CH1 Digital Loop via codec part CH2
Reserved
7.3.13
CRAM Control (CCR) and Status (CSR) Register
The programming of the CRAM Control Register (CCR) and the CRAM Status Register (CSR) is intended for a back-up procedure for the direct access to individual CRAM coefficients. A detailed description can be found in chapter 4.8.2.1.
Data Sheet
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Detalled Register Description CRAM Status Register (CSR) Value after reset: 00H 7 CCR DCA 0 0 DCA BSYB CBADR 0 RD (6FH)
... DSP CRAM Access
Read-back of the programmed value BSYB ... Busy Back-up Procedure
0: Momentary there is no transfer of CRAM data to the temporary area running. CRAM access via microcontroller interface is possible 1: Transfer of the CRAM block is running. CRAM access via microcontroller interface is not allowed CBADR ... CRAM Block Address
Read-back of the programmed value CRAM Control Register (CCR) Value after reset: 00H 7 CCR DCA 0 0 DCA SBP CBADR 0 WR (6FH)
... DSP CRAM Access
0: The normal CRAM area (80H tp FFH) is accessed by the codec DSP 1: The temporary CRAM area (coefficient block with 8 bytes corresponding to the COP_x sequences) is accessed by the codec DSP. The switching to the temporary CRAM block happens as soon as the transfer of the block has completed (BSYB = '0') SBP ... Start Back-up Procedure
0: No back-up is initiated 1: A transition to SBP = '1' starts the back-up of the CRAM block into the temporary CRAM area CBADR ... CRAM Block Address
Address of a coefficient block with 8 bytes corresponding to the COP_x sequences (x=0...F) of the codec programming sequences
Data Sheet
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Detalled Register Description 7.3.14 CRAM (Coefficient RAM)
Address Mnemonic Description 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH T1 GD1 G1 F1 GTX GTR T2 GD2 G2 F2 FD T3 GD3 G3 F3 GE A2 A1 K Reserved Reserved Beat tone time lower byte Beat tone time higher byte Trapezoid generator amplitude Tone generator amplitude Tone generator frequency lower byte Tone generator frequency higher byte Level adjustment for transmit path Level adjustment for receive path Beat tone time span lower byte Beat tone time span higher byte Trapezoid generator amplitude Tone generator amplitude Tone generator frequency lower byte Tone generator frequency higher byte Dual tone frequency lower byte Dual tone frequency higher byte Beat tone time span lower byte Beat tone time span higher byte Trapezoid generator amplitude Tone generator amplitude Tone generator frequency lower byte Tone generator frequency higher byte Saturation amplification Bandwidth Center frequency Attenuation of the stop-band Reserved Reserved Reserved Reserved
Data Sheet
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Detalled Register Description Address Mnemonic Description A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H
Data Sheet
TOFF TON ATT2R ATT1R GR GX GZ FX
Turn-off period of the tone generator lower byte Turn-off period of the tone generator higher byte Turn-on period of the tone generator lower byte Turn-on period of the tone generator higher byte Reserved Reserved Reserved Reserved Reserved Reserved Conferencing attenuation CH2R Conferencing attenuation CH1R Receive gain lower byte Receive gain higher byte Transmit gain lower byte Transmit gain higher byte Reserved Reserved Sidetone gain lower byte Sidetone gain higher byte Reserved Reserved Reserved Reserved Transmit correction filter coefficients part 8 Transmit correction filter coefficients part 7 Transmit correction filter coefficients part 6 Transmit correction filter coefficients part 5 Transmit correction filter coefficients part 4 Transmit correction filter coefficients part 3 Transmit correction filter coefficients part 2 Transmit correction filter coefficients part 1 Receive correction filter coefficients part 12 Receive correction filter coefficients part 11 Receive correction filter coefficients part 10 Receive correction filter coefficients part 9 Transmit correction filter coefficients part 12 Transmit correction filter coefficients part 11 Transmit correction filter coefficients part 10 Transmit correction filter coefficients part 9
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FR
FX
PSB 21391 PSB 21393
Detalled Register Description Address Mnemonic Description C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH
Data Sheet
FR
Receive correction filter coefficients 8 Receive correction filter coefficients 7 Receive correction filter coefficients 6 Receive correction filter coefficients 5 Receive correction filter coefficients 4 Receive correction filter coefficients 3 Receive correction filter coefficients 2 Receive correction filter coefficients 1 Switching time Decay speed Wait time Echo time (line side) Echo time (acoustic side) Attenuation programmed in GHR or GHX Gain of line echo Gain of acoustic echo Peak decrement when noise is detected (line side) Reserve when noise is detected (line side) Peak decrement when speech is detected (line side) Reserve when speech is detected (line side) Peak decrement when noise is detected (acoustic side) Reserve when noise is detected (acoustic side) Peak decrement when speech is detected (acoustic side) Reserve when speech is detected (acoustic side) Reserved Time constant LP1 (receive) Time constant LP1 (transmit) Limitation for LP2 (receive) Limitation for LP2 (transmit) Level offset up to detected noise (receive) Level offset up to detected noise (transmit) Starting level of the logarithmic amplifiers Time constant LP2 for noise (receive) Time constant LP2 for signal (receive) Time constant PD for noise (receive) Time constant PD for signal (receive) Time constant LP2 for noise (transmit) Time constant LP2 for signal (transmit) Time constant PD for noise (transmit) Time constant PD for signal (transmit)
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SW DS TW ETLE ETAE ATT GLE GAE PDNLE GDNLE PDSLE GDSLE PDNAE GDNAE PDSAE GDSAE LP1R LP1X LP2LR LP2LX OFFR OFFX LIM LP2NR LP2SR PDNR PDSR LP2NX LP2SX PDNX PDSX
PSB 21391 PSB 21393
Detalled Register Description Address Mnemonic Description F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH AGIX NOISX TMLX TMHX AGX AAX COMX LGAX AGIR NOISR TMLR TMHR AGR AAR COMR LGAR Initial AGC gain transmit Threshold for AGC-reduction by background noise Settling time constant for lower levels Settling time constant for higher levels Gain range of automatic control Attenuation range of automatic control Compare level rel. to max. PCM-value Loudness gain adjustment Initial AGC attenuation/gain receive Threshold for AGC-reduction by background noise Settling time constant for lower levels Settling time constant for higher lower levels Gain range of automatic control Attenuation range of automatic control Compare level rel. to max. PCM-value Loudness gain adjustment
Data Sheet
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Electrical Characteristics 8 8.1 8.1.1 Electrical Characteristics Electrical Characteristics (general) Absolute Maximum Ratings Symbol min. Storage temperature Input/output voltage on any pin with respect to ground Maximum voltage on any pin with respect to ground Limit Values max. 150 C V V - 65 - 0.3 Unit
Parameter
TSTG VS
Vmax
VDD + 0.3
7
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 8.1.2 DC-Characteristics Symbol Limit Values min. H-input level (except pin XTAL1) L-input level (except pin XTAL1) H-output level (except pin XTAL2) L-output level (except pin XTAL2, DU, DD) L-output level (pins DU,DD) H-input level (pin XTAL1) typ. max. 2.0 - 0.3 2.4 0.45 Unit Test Condition V V V V
VDD = 5 V 5 % or 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C
Parameter
VIH VIL VOH VOL
VDD +
0.3 0.8
IO = -400 A IO = 2 mA
VOL VIH VDD0.5
0.45
V V
IO = 7mA
VDD
Data Sheet
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Electrical Characteristics 8.1.2 DC-Characteristics (cont'd) Symbol Limit Values min. L-input level (pin XTAL1) Input leakage current Output leakage current (all pins except SX1,2,SR1,2,XTAL1,2 BGREF, Vref) 8.1.3 grounded. Table 26 Parameter Input Capacitance I/O Capacitance Output Capacitance against VSS Load Capacitance Symbol CIN CI/O COUT CL Limit Values Unit min. max. 7 7 25 60 pF pF pF pF All pins except LIa and LIb pins LIa, LIb pins XTAL1,2 Remarks Capacitances typ. max. 0.4 1 1 V A A 0V< VINVDD = 5 V 5 % or 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C
Parameter
VIL ILI ILO
VDD = 5 V 5 %, 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C; fc = 1 MHz; unmeasured pins
Data Sheet
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Electrical Characteristics 8.1.4 Oscillator Specification
Recommended Oscillator Circuit
33 pF CL
41
XTAL1
External Oscillator Signal
41
XTAL1
15.36 MHz 7.68 MHz
33 pF CL Crystal Oscillator Mode
42
XTAL2
N.C.
42
XTAL2
Driving from External Source
ITS09659
Figure 83 Oscillator Circuit Crystal Specification Parameter Frequency Frequency calibration tolerance Load capacitance Oscillator mode Resistance R1 CL Symbol f Limit Values 15.36 max. 100 max. 40 fundamental max. 50 Unit MHz ppm pF
Note: The load capacitance CL depends on the recommendation of the crystal specification. Typical values for CL are 22...33 pF. XTAL1 Clock Characteristics (external oscillator input) Parameter Duty cycle Limit Values min. 2:3 max. 3:2
Data Sheet
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Electrical Characteristics 8.1.5 AC Characteristics
VDD = 5 V 5 % or 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C
Inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC testing input/output waveforms are shown in figure 84.
2.4 2.0 Test Points 0.8 0.45 0.8 2.0 Device Under Test C Load = 100 pF
ITS09660
Figure 84 Input/Output Waveform for AC Tests
Data Sheet
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Electrical Characteristics 8.1.6 IOM-2 Interface Timing
FSC (0) tIIS tFSD
DCL (0) tIIH DU/DD (I) tIOD DU/DD (0)
tSDD SDS1/2 tBCD BCL (0) tBCD
ITD09663.vsd
Figure 85 IOM(R) Timing
Data Sheet
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Electrical Characteristics
Parameter IOM output data delay IOM input data setup IOM input data hold FSC strobe delay Strobe signal delay BCL / FSC delay Frame sync setup Frame sync hold Frame sync width DCL Clock Characteristics
Symbol tIOD tIIS tIIH tFSD tSDD tBCD tFSS tFSH tFSW
Limit Values min. 20 20 -130 120 100 50 30 40 typ. max. 100
Unit ns ns ns ns ns ns ns ns ns
0.9 VDD 0.1 VDD
Figure 86 Definition of Clock Period and Width Symbol min. tPO tWHO tWLO 585 260 260 Limit Values typ. 651 325 325 max. 717 391 391 ns ns ns osc 100 ppm osc 100 ppm osc 100 ppm Unit Test Condition
Data Sheet
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Electrical Characteristics 8.1.7 8.1.7.1 Microcontroller Interface Timing Serial Control Interface (SCI) Timing
t1 t4 CS t2 t3 t5
SCLK t6 SDR t8 SDX t10 t7 t9
Figure 87 SCI Interface Parameter SCI Interface SCLK cycle time SCLK high time SCLK low time CS setup time CS hold time SDR setup time SDR hold time SDX data out delay CS high to SDX tristate SCLK to SDX active Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Limit values Min 500 100 100 0 10 40 40 80 40 80 Max ns ns ns ns ns ns ns ns ns ns Unit
Data Sheet
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Electrical Characteristics 8.1.8 Reset
Table 27 Reset Signal Characteristics Parameter Length of active low state Symbol tRST Limit Values min. 4 2 x DCL clock cycles 8.1.9 Undervoltage Detection Characteristics ms Power On/Power Down to Power Up (Standby) During Power Up (Standby) Unit Test Conditions
Figure 88 Undervoltage Control Timing
Data Sheet
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Electrical Characteristics
VDD = 5 V 5 % or 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C
Parameter Detection Threshold Detection Threshold Hysteresis Max. rising/falling VDD edge for activation/ deactivation Min. operating voltage Delay for activation of RST Delay for deactivation of RST Symbol min. VDET VDET VHys dVDD/dt 2.7 4.2 Limit Values typ. 2.8 4.35 max. 2.9 4.5 0.1 V V V/s Unit Test Condition
VDD= 3.3V 5 % VDD= 5V 5 %
VDD/40 VDD/35 VDD/30 V
VDDmin tACT tDEACT
1.5 10 56
V s ms
Data Sheet
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Electrical Characteristics 8.2 Electrical Characteristics (Transceiver)
DC Characteristics
VDD = 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C
Parameter Power supply currentpower-up (after reset) Power supply currentpower down Power supply currentTranceiver active, sending continous pulses Power supply currentTranceiver active, sending single pulses Power supply currentcodec powered up Power supply currenttone generation active (single tone generated) DC Characteristics Symbol IDUAR IDPD IDTCP Limit Values min. typ. 6 1.2 9 max. mA mA mA 100 Ohms load on the line Unit Test Condition
IDTSP
8
mA
100 Ohms load on the line
IDCPU IDTG
7 19
mA mA -18.5 dB amplification 50 Ohms load
VDD = 5 V 5 % , VSS = 0 V; TA = 0 to 70 C
Parameter Power supply currentpower-up (after reset) Power supply currentpower down Power supply currentTranceiver active, sending continous pulses Symbol IDUAR IDPD IDTCP Limit Values min. typ. 6.5 1.4 21.0 max. mA mA mA 100 Ohms load on the line Unit Test Condition
Data Sheet
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Electrical Characteristics DC Characteristics (cont'd)
VDD = 5 V 5 % , VSS = 0 V; TA = 0 to 70 C
Parameter Power supply currentTranceiver active, sending single pulses Power supply currentcodec powered up Power supply currenttone generation active (single tone generated) DC Characteristics Symbol IDTSP Limit Values min. typ. 10.5 max. mA 100 Ohms load on the line Unit Test Condition
IDCPU IDTG
9.0 27.0
mA mA -18.5 dB amplification 50 Ohms load
VDD = 5 V 5 % or 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C
Parameter Symbol Limit Values Unit Test Condition min Transmitter output impedance Receiver input impedance ZX 10 max 30 IOUT = 40mA LIa, LIb Remarks
ZR
20
k
Transmitter inactive
LIa, LIb single ended
x
Data Sheet
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Electrical Characteristics 8.3
xxxxxxxxxxxxxxxxxx
Electrical Characteristics (Codec) DC Characteristics Symbol Limit Values min. typ. 9 max. mA fTR = 400 Hz square wave; ALS = -3.5dB Unit Test Condition
8.3.1
VDD = 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C
Parameter Power supply current in Emergency Ringing Mode (AFE) Handset Mode (AFE) Speakerphone Mode (AFE) Loudhearing Mode (AFE)
ITR IHS ISP ILH
10 11
mA mA
13
mA
VDD = 5 V 5 %, VSS = 0 V; TA = 0 to 70 C
Parameter Power supply current in Emergency Ringing Mode (AFE) Handset Mode (AFE) Speakerphone Mode (AFE) Loudhearing Mode (AFE) Symbol Limit Values min. typ. 12 max. mA fTR = 400 Hz square wave; ALS = -3.5dB Unit Test Condition
ITR IHS ISP ILH
13 14
mA mA
16
mA
Note: Operating power dissipation is measured with all analog outputs open. All analog inputs are set to VREF. The digital input signal (pin DD) is set to an idle code.
Data Sheet
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Electrical Characteristics Transmission Characteristics VDD = 5 V 5 % or 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C Parameter Overall programming range (With specified transmission characteristics) Limit Values min. - 21.5 - 21.5 0 0 Programmable AFE gain Attenuation Distortion @ 0 dBm0 - 0.5 - 1.0 0 - 0.25 - 0.25 - 0.25 - 0.25 0 max. 11.5 2.5 36 24 0.5 1.0 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB s s s s dB dB dB 0.3 0.6 1.6 dB dB dB Receive: loudspeaker earpiece Transmit: differential inputs single ended input step accuracy overall accuracy < 200 Hz 200 - 300 Hz 300 - 2400 Hz 2400 - 3000 Hz 3000 - 3400 Hz > 3400 Hz receive (TGSR.ERA=0): 4.6 kHz 8.0 kHz receive(TGSR.ERA=1): 4.6 kHz 8.0 kHz transmit: 4.6 kHz 8.0 kHz TGSR.ERA=0 500 - 600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz 0 to - 30 dBm0 - 40 dBm0 - 45 dBm0 3 to - 40 dBm0 - 40 to - 50 dBm0 - 50 to - 55 dBm0 Unit Test Condition
0.25 0.45 0.9
Out-of-band signals - 35 - 45 - 45 - 65 - 35 - 40 Group delay distortion @ 0 dBm0 1) 750 380 130 750 35 29 24 - 0.3 - 0.6 - 1.6
Signal-to-total distortion (method 2, sinewave 1kHz) Gain tracking (method 2) @ - 10 dBm0
Data Sheet
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Electrical Characteristics Transmission Characteristics (cont'd) VDD = 5 V 5 % or 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C Parameter Idle-channel noise Cross-talk Limit Values min. max. - 75 - 66 - 66 dBm0 dBm0 dB receive (A-Law; Psoph.) transmit (A-Law; Psoph.) Reference: 0 dBm0 Unit Test Condition
1) Delay measurements include delays through the A/D and D/A with all features filters FX, GX, FR and GR disabled.
8.3.2
Analog Front End Input Characteristics
VDD = 5 V 5 % or 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C
Parameter AMI-input impedance AMI-input voltage swing with specified transmission characteristics Symbol Limit Values min. typ max. k 19 38 1.2 2.4 mVp mVp Vp Vp Vp Vp 300 - 3400 Hz 36 dB; VDD=3.3V 36 dB; VDD=5V differential; 0 dB; VDD=3.3V 0 dB; VDD=5V single ended; 0 dB; VDD=3.3V 0 dB; VDD=5V 12.5 15 Unit Test Condition
ZAMI VAMI VAMI_dif
VAMI_single
0.75 1.67
8.3.3
Analog Front End Output Characteristics 300 - 3400 Hz 300 - 3400 Hz Load measured from VREF to VSSA
VDD = 5 V 5 % or 3.3 V 5 %, VSS = 0 V; TA = 0 to 70 C AHO-output impedance ZAHO 2 ALS-output impedance ZALS 2 VREF output impedance ZVREF 7 10 VVREF BGREF output impedance ZBGREF
VREF output voltage 2.25 2.4 200 300 2.55 400 V k
IVREF = - 2 mA
Data Sheet
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Electrical Characteristics Parameter Symbol Limit Values min. typ max. Unit Test Condition
VDD = 5V 5 %
AHO-output voltage swing
VAHO
3.2
Vpk
Load (200) measured from HOP to HON Load (50) measured from LSP to LSN
ALS-output voltage swing
VALS
3.2
Vpk
VDD = 3.3 V 5 %
AHO-output voltage swing
VAHO
1.6
Vpk
Load (200) measured from HOP to HON Load (25) measured from LSP to LSN
ALS-output voltage swing
VALS
1.6
Vpk
The maximum output voltage swing corresponds to the maximum incoming PCM-code ( 127)
Data Sheet
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Package Outlines 9 Package Outlines
P-MQFP-44-1 (SMD) (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 242
Dimensions in mm 2001-03-07
GPM05622
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